LPC47M112_07 SMSC [SMSC Corporation], LPC47M112_07 Datasheet - Page 126

• Manufacturer Part Number: LPC47M112_07
• Description: Enhanced Super I/O Controller with LPC Interface
• Manufacturer: SMSC [SMSC Corporation]

Enhanced Super I/O Controller with LPC Interface
Datasheet
When D0 = “0”, the DCC bits determine the F
state of the DCC bits.
25.1.2 FAN CONTROL REGISTER
The Fan Control Register is located at 0x58 from base I/O in Logical Device A. The bits are defined below. See the
register description in the Runtime Registers section.
25.1.2.1
Fan x Count Divisor bit in Fan Control Register is used to determine fan tachometer count. The choices for the
divisor are 1, 2, 4 and 8. See “Fan Tachometer Input” section.
25.1.2.2
The Fan x Clock Multiplier bit is used with the Fan x Clock Source Select bit in the Fan Control Register and the Fan
x Clock Select bit in Fan register to determine the F
When the Fan x Clock Multiplier bit = “0”, no clock multiplier is used. When the Fan x Clock Multiplier bit = “1”, the
clock speed determined by the Fan x Clock Source Select bit is doubled.
25.1.2.3
The Fan x Clock Source Select and the Fan x Clock Multiplier bits in the Fan Control register is used with The Fan x
Clock Select bit in the Fan x registers to determine the fan speed F
25.2
The LPC47M112 implements fan tachometer inputs for signals from fans equipped with tachometer outputs. The part
can generate both a PME and an SMI when the fan speed drops below a predetermined value. See description
below.
The clock source for the tachometer count is the 32.768kHz oscillator. The Fan Tachometer Inputs gate a divided
down version of the 32.768kHz oscillator for one period of the Fan signal into an 8-bit counter (maximum count is
255).
The clock source is determined by the CLK32_PRSN bit in the CLOCKI32 register in logical device A. It is either the
32.768kHz clock from the CLKI32 pin or an internal 32.765kHz clock derived from the 14MHz clock.
The fan tachometer input signal and clock source is shown below.
The counter is reset by the rising edge of each pulse (and by writing the preload register). The counter does not
wrap; if it reaches 0xFF, it remains at 0xFF until it is reset by the next pulse.
SMSC DS – LPC47M112
Fan Tachometer Inputs
Fan x Count Divisor, Bits D7-D6 / D5-D4
Fan x Clock Multiplier, Bits D3 / D2
Fan x Clock Source Select, Bits D1 / D0
Fan
Tachometer
Input
Clock Source
for Counter
T
P
T
R
DATASHEET
OUT
T
T
F = 32.786kHz ÷ Divisor
R
P
= Revolution Time = 60/RPM (sec)
= Pulse Time = T
duty cycle. When D0 = 1, F
OUT
(Two Pulses Per Revolution)
.
Page 126
R
/2
OUT
. See Table 58 above.
OUT
is always high, regardless of the
Rev. 02-16-07