LPC47M112_07 SMSC [SMSC Corporation], LPC47M112_07 Datasheet - Page 5

• Manufacturer Part Number: LPC47M112_07
• Description: Enhanced Super I/O Controller with LPC Interface
• Manufacturer: SMSC [SMSC Corporation]

Enhanced Super I/O Controller with LPC Interface
Datasheet
FIGURE 6 – MOUSE LATCH.....................................................................................................................................112
FIGURE 7 -GPIO FUNCTION ILLUSTRATION .........................................................................................................117
FIGURE 8 - POWER-UP TIMING ..............................................................................................................................178
FIGURE 9A - INPUT CLOCK TIMING .......................................................................................................................178
FIGURE 10 - OUPUT TIMING MEASUREMENT CONDITIONS, LPC SIGNALS......................................................180
FIGURE 11 – INPUT TIMING MEASUREMENT CONDITIONS, LPC SIGNALS.......................................................180
FIGURE 12 – I/O WRITE ...........................................................................................................................................181
FIGURE 13 – I/O READ.............................................................................................................................................181
FIGURE 14 – DMA REQUEST ASSERTION THROUGH NLDRQ ............................................................................182
FIGURE 15 – DMA WRITE (FIRST BYTE) ................................................................................................................182
FIGURE 16 – DMA READ (FIRST BYTE)..................................................................................................................182
FIGURE 17 – FLOPPY DISK DRIVE TIMING (AT MODE ONLY) .............................................................................183
FIGURE 18 – EPP 1.9 DATA OR ADDRESS WRITE CYCLE ...................................................................................184
FIGURE 19 – EPP 1.9 DATA OR ADDRESS READ CYCLE ....................................................................................185
FIGURE 20 – EPP 1.7 DATA OR ADDRESS WRITE CYCLE ...................................................................................186
FIGURE 21 – EPP 1.7 DATA OR ADDRESS READ CYCLE ....................................................................................187
FIGURE 22 - PARALLEL PORT FIFO TIMING...........................................................................................................189
FIGURE 23 - ECP PARALLEL PORT FORWARD TIMING ........................................................................................190
FIGURE 24 - ECP PARALLEL PORT REVERSE TIMING..........................................................................................191
FIGURE 25 - IRDA RECEIVE TIMING.......................................................................................................................192
FIGURE 26 - IRDA TRANSMIT TIMING ....................................................................................................................193
FIGURE 27 - AMPLITUDE SHIFT KEYED IR RECEIVE TIMING..............................................................................194
FIGURE 28 - AMPLITUDE SHIFT KEYED IR TRANSMIT TIMING ...........................................................................195
FIGURE 29 – SETUP AND HOLD TIME....................................................................................................................196
FIGURE 30 – SERIAL PORT DATA ..........................................................................................................................196
FIGURE 31 – JOYSTICK POSITION SIGNAL ...........................................................................................................197
FIGURE 32 – JOYSTICK BUTTON SIGNAL .............................................................................................................197
FIGURE 33 – KEYBOARD/MOUSE RECEIVE/SEND DATA TIMING .......................................................................198
FIGURE 34– MIDI DATA BYTE .................................................................................................................................199
FIGURE 35 – FAN OUTPUT TIMING ........................................................................................................................199
FIGURE 36 – FAN TACHOMETER INPUT TIMING ..................................................................................................200
FIGURE 37 – LED OUTPUT TIMING ........................................................................................................................200
FIGURE 38 - 100 PIN 14X20MM QFP PACKAGE OUTLINE, 3.2 MM FOOTPRINT.................................................201
FIGURE 39 - XNOR-CHAIN TEST STRUCTURE......................................................................................................202
List of Tables
Table 1 - Super I/O Block Addresses ...........................................................................................................................20
Table 2 - Status, Data and Control Registers...............................................................................................................25
Table 3 - Tape Select Bits.............................................................................................................................................29
Table 4 - Internal 2 Drive Decode - Normal ...................................................................................................................29
Table 5 - Internal 2 Drive Decode - Drives 0 and 1 Swapped ........................................................................................30
Table 6 - Drive Type ID.................................................................................................................................................30
Table 7 - Precompensation Delays ..............................................................................................................................31
Table 8 - Data Rates ....................................................................................................................................................31
Table 9 - DRVDEN Mapping ........................................................................................................................................32
Table 10 - Default Precompensation Delays ................................................................................................................32
Table 11 - FIFO Service Delay......................................................................................................................................34
Table 12 - Status Register 0 .........................................................................................................................................36
Table 13 - Status Register 1 .........................................................................................................................................37
Table 14 - Status Register 2 ........................................................................................................................................37
Table 15 - Status Register 3 ........................................................................................................................................38
Table 16 – Description of Command Controls .............................................................................................................41
Table 17 - Instruction Set .............................................................................................................................................44
Table 18 - Sector Sizes ................................................................................................................................................51
Table 19 - Effects of MT and N Bits ..............................................................................................................................51
Table 20 - Skip Bit vs Read Data Command.................................................................................................................51
Table 21 - Skip Bit vs. Read Deleted Data Command ...................................................................................................52
Table 22 - Result Phase...............................................................................................................................................53
Table 23 - Verify Command Result Phase ....................................................................................................................54
Table 24 - Typical Values for Formatting.......................................................................................................................55
SMSC DS – LPC47M112
Page 5
Rev. 02-16-07
DATASHEET