LPC47M112_07 SMSC [SMSC Corporation], LPC47M112_07 Datasheet - Page 73

• Manufacturer Part Number: LPC47M112_07
• Description: Enhanced Super I/O Controller with LPC Interface
• Manufacturer: SMSC [SMSC Corporation]

ADDR = 7
ADDR = 0
ADDR = 1
DLAB = 1
Enhanced Super I/O Controller with LPC Interface
Datasheet
SMSC DS – LPC47M112
DLAB = 1
ADDRESS*
REGISTER
*DLAB is Bit 7 of the Line Control Register (ADDR = 3).
Note 1: Bit 0 is the least significant bit. It is the first bit serially transmitted or received.
Note 2: When operating in the XT mode, this bit will be set any time that the transmitter shift register is
empty.
Note 3: This bit no longer has a pin associated with it.
Note 4: When operating in the XT mode, this register is not available.
Note 5: These bits are always zero in the non-FIFO mode.
Note 6: Writing a one to this bit has no effect. DMA modes are not supported in this chip.
Note 7: The UART1 and UART2 FCR’s are shadowed in the UART1 FIFO Control Shadow Register
Data Bit 2
Data Bit 2
Enable
Receiver Line
Status
Interrupt
(ELSI)
Interrupt ID Bit Interrupt ID Bit
XMIT FIFO
Reset
Number of
Stop Bits
(STB)
OUT1
(Note 3)
Parity Error
(PE)
Trailing Edge
Ring Indicator
(TERI)
Bit 2
Bit 2
Bit 10
BIT 2
(runtime register at offset 0x20) and UART2 FIFO Control Shadow Register (runtime register at
offset 0x21).
Table 32 - Register Summary for an Individual UART Channel (continued)
Scratch Register (Note 4)
Divisor Latch (LS)
Divisor Latch (MS)
Data Bit 3
Data Bit 3
Enable
MODEM
Status
Interrupt
(EMSI)
(Note 5)
DMA Mode
Select
6)
Parity Enable
(PEN)
OUT2
(Note 3)
Framing Error
(FE)
Delta Data
Carrier Detect
(DDCD)
Bit 3
Bit 3
Bit 11
REGISTER NAME
BIT 3
(Note
Data Bit 4
Data Bit 4
0
0
Reserved
Even Parity
Select (EPS)
Loop
Break
Interrupt (BI)
Clear to Send
(CTS)
Bit 4
Bit 4
Bit 12
BIT 4
DATASHEET
Data Bit 5
Data Bit 5
0
0
Reserved
Stick Parity
0
Transmitter
Holding
Register
(THRE)
Data Set
Ready (DSR)
Bit 5
Bit 5
Bit 13
Page 73
BIT 5
REGISTER
SYMBOL
SCR
DLM
DDL
Data Bit 6
Data Bit 6
0
FIFOs
Enabled
(Note 5)
RCVR Trigger
LSB
Set Break
0
Transmitter
Empty (TEMT)
(Note 2)
Ring Indicator
(RI)
Bit 6
Bit 6
Bit 14
BIT 6
Bit 0
Bit 0
Bit 8
BIT 0
Data Bit 7
Data Bit 7
0
FIFOs
Enabled
(Note 5)
RCVR Trigger
MSB
Divisor Latch
Access Bit
(DLAB)
0
Error in RCVR
FIFO (Note 5)
Data Carrier
Detect (DCD)
Bit 7
Bit 7
Bit 15
BIT 7
Bit 1
Bit 1
Bit 9
BIT 1
Rev. 02-16-07