LPC47M112_07 SMSC [SMSC Corporation], LPC47M112_07 Datasheet - Page 124

• Manufacturer Part Number: LPC47M112_07
• Description: Enhanced Super I/O Controller with LPC Interface
• Manufacturer: SMSC [SMSC Corporation]

Enhanced Super I/O Controller with LPC Interface
Datasheet
The state machine will reset if there is a period where the clock remains high for more than one keyboard clock
period (115-145usec) in the middle of the transmission (i.e., before clock 11). This is to prevent the generation of a
false PME.
The CLK32_PRSN bit (bit 0 of the CLOCKI32 register at 0xF0 in Logical Device A) will determine the clock source for
this feature when the part is powered by VCC. If the external 32kHz clock is not connected, the 32kHz internal signal
is derived from the 14MHz clock when VCC is active. Use the 32kHz clock for this feature when the part is under
trickle power. This feature will not work when the part is under trickle power (VCC removed) if the external 32kHz
clock is not connected.
The SPEKEY_EN bit at bit 1 of the CLOCKI32 register at 0xF0 in Logical Device A is used to control this feature.
This bit is used to turn the logic for this feature on and off. It will disable the 32 kHz clock input to the logic. The logic
will draw no power when disabled. The bit is defined as follows:
0= “Wake on specific key” logic is on (default)
1= “Wake on specific key” logic is off
Note: The generation of a PME for this event is controlled by the PME enable bit (located in the PME_EN1 register at
bit 5) when the logic for feature is turned on.
SMSC DS – LPC47M112
Page 124
Rev. 02-16-07
DATASHEET