LPC47M112_07 SMSC [SMSC Corporation], LPC47M112_07 Datasheet - Page 75

• Manufacturer Part Number: LPC47M112_07
• Description: Enhanced Super I/O Controller with LPC Interface
• Manufacturer: SMSC [SMSC Corporation]

Enhanced Super I/O Controller with LPC Interface
Datasheet
14 INFRARED INTERFACE
The infrared interface provides a two-way wireless communications port using infrared as a transmission medium. Two
IR implementations have been provided for the second UART in this chip (logical device 5), IrDA and Amplitude Shift
Keyed IR. The IR transmission can use the standard UART2 TXD2 and RXD2 pins or optional IRTX2 and IRRX2 pins.
These can be selected through the configuration registers.
IrDA 1.0 allows serial communication at baud rates up to 115.2 kbps. Each word is sent serially beginning with a zero
value start bit. A zero is signaled by sending a single IR pulse at the beginning of the serial bit time. A one is signaled
by sending no IR pulse during the bit time. Please refer to the AC timing for the parameters of these pulses and the
IrDA waveform.
The Amplitude Shift Keyed IR allows asynchronous serial communication at baud rates up to 19.2K Baud. Each word is
sent serially beginning with a zero value start bit. A zero is signaled by sending a 500kHz waveform for the duration of
the serial bit time. A one is signaled by sending no transmission during the bit time. Please refer to the AC timing for the
parameters of the ASK-IR waveform.
If the Half Duplex option is chosen, there is a time-out when the direction of the transmission is changed. This time-out
starts at the last bit transferred during a transmission and blocks the receiver input until the timeout expires. If the
transmit buffer is loaded with more data before the time-out expires, the timer is restarted after the new byte is
transmitted. If data is loaded into the transmit buffer while a character is being received, the transmission will not start
until the time-out expires after the last receive bit has been received. If the start bit of another character is received
during this time-out, the timer is restarted after the new character is received. The IR half duplex time-out is
programmable via CRF2 in Logical Device 5. This register allows the time-out to be programmed to any value between 0
and 10msec in 100usec increments.
IR Transmit Pins
The following description pertains to the IRTX and IRTX2 pins of the LPC47M112.
Following a VTR POR, the IRTX and IRTX2 pins will be output and low. They will remain low until one of the
following conditions are met:
IRTX2/GP35 Pin. This pin defaults to the IRTX2 function.
1.
2.
GP53/TXD2 (IRTX) Pin. This pin defaults to the GPIO output function.
1.
2.
The TXD2_MODE bit is implemented for modems that do not assert the ring indicator pin when TXD2 is sensed low. If
required, this bit should be used as follows:
The IRTX2 pin is not affected by the TXD2_MODE bit.
SMSC DS – LPC47M112
This pin will remain low following a VCC POR until serial port 2 is enabled by setting the activate bit, at which
time the pin will reflect the state of the IR transmit output of the Serial Port 2 block.
This pin will remain low following a VCC POR until the GPIO output function is selected for the pin, at which time
the pin will reflect the state of the GPIO data bit if it is configured as an output.
This pin will remain low following a VCC POR until the TXD2 function is selected for the pin AND serial port 2 is
enabled by setting the activate bit, at which time the pin will reflect the state of the transmit output of serial port 2.
Following a VCC POR, setting the TXD2_MODE bit (bit 5 in Serial Port 2 Mode Register, 0xF0 in Logical Device
5 Configuration Registers) to ‘1’ will change the state of the TXD2 pin from low to tristate, regardless of the
function selected on the pin (GP10 or TXD2), regardless of the state of the activate bit for serial port 2 and
regardless of the state of VCC. When VCC is removed from the part while the TXD2_MODE bit is set to ‘1’, the
TXD2 pin will remain tristate unless a VTR POR occurs, which will reset the TXD2_MODE bit.
This pin will remain low following a VCC POR until the corresponding GPIO data bit (GP5 register bit 3) is set or
the polarity bit in the GP53 control register is set.
When the activate bit for serial port 2 is cleared prior to entering a sleep state, set the TXD2_MODE bit.
When the activate bit for serial port 2 is set, upon exiting a sleep state, clear the TXD2_MODE bit.
DATASHEET
Page 75
Rev. 02-16-07