LPC47M112_07 SMSC [SMSC Corporation], LPC47M112_07 Datasheet - Page 40

• Manufacturer Part Number: LPC47M112_07
• Description: Enhanced Super I/O Controller with LPC Interface
• Manufacturer: SMSC [SMSC Corporation]

Enhanced Super I/O Controller with LPC Interface
Datasheet
DMA Mode - Transfers from the Host to the FIFO.
The FDC generates a DMA request cycle when entering the execution phase of the data transfer commands. The DMA
controller must respond by placing data in the FIFO. The DMA request remains active until the FIFO becomes full. The
DMA request cycle is reasserted when the FIFO has <threshold> bytes remaining in the FIFO. The FDC will terminate
the DMA cycle after a TC, indicating that no more data is required.
Data Transfer Termination
The FDC supports terminal count explicitly through the TC pin and implicitly through the underrun/overrun and end-of-
track (EOT) functions. For full sector transfers, the EOT parameter can define the last sector to be transferred in a
single or multi-sector transfer.
If the last sector to be transferred is a partial sector, the host can stop transferring the data in mid-sector, and the FDC
will continue to complete the sector as if a TC cycle was received. The only difference between these implicit functions
and TC cycle is that they return "abnormal termination" result status. Such status indications can be ignored if they were
expected.
Note that when the host is sending data to the FIFO of the FDC, the internal sector count will be complete when the FDC
reads the last byte from its side of the FIFO. There may be a delay in the removal of the transfer request signal of up to
the time taken for the FDC to read the last 16 bytes from the FIFO. The host must tolerate this delay.
Result Phase
The generation of the interrupt determines the beginning of the result phase. For each of the commands, a defined set
of result bytes has to be read from the FDC before the result phase is complete. These bytes of data must be read out
for another command to start.
RQM and DIO must both equal "1" before the result bytes may be read. After all the result bytes have been read, the
RQM and DIO bits switch to "1" and "0" respectively, and the CB bit is cleared, indicating that the FDC is ready to accept
the next command.
SMSC DS – LPC47M112
Page 40
Rev. 02-16-07
DATASHEET