LPC47M112_07 SMSC [SMSC Corporation], LPC47M112_07 Datasheet - Page 129

• Manufacturer Part Number: LPC47M112_07
• Description: Enhanced Super I/O Controller with LPC Interface
• Manufacturer: SMSC [SMSC Corporation]

Enhanced Super I/O Controller with LPC Interface
Datasheet
26 SECURITY FEATURE
The following register describes the functionality to support security in the LPC47M112.
26.1
The GPIO pin GP43 is used for the Device Disable Register Control (DDRC) function. Setting bits[3:2] of the GP43
configuration register to ‘01’, selects the DDRC function for the GP43 pin. When bits[3:2]=01 the GP43 pin is an
input, with non-inverted polarity. Bits[3:2] cannot be cleared by writing to these bits; they are cleared by VTR POR,
VCC POR and Hard Reset. That is, when the DDRC function is selected for this pin, it cannot be changed, except by a
VCC POR, hard reset or VTR POR.
When the DDRC function is selected for GP43, the Device Disable register is controlled by the value of the GP43 pin
as follows:
26.2
The Device Disable Register is located in the PME register block at offset 0x22 from the PME_BLK base I/O address
in logical device A. Writes to this register are blocked when the GP43 pin is configured for the Device Disable
Register Control function (GP43 configuration register bit 2 =1) and the GP43 pin is high.
The configuration register for the device disable register is defined in the “Runtime Registers” section.
SMSC DS – LPC47M112
If the GP43 pin is high, the Device Disable Register is Read-Only.
If the GP43 pin is low, the Device Disable Register is Read/Write.
GPIO Device Disable Register Control
Device Disable Register
DATASHEET
Page 129
Rev. 02-16-07