LPC47M112_07 SMSC [SMSC Corporation], LPC47M112_07 Datasheet - Page 70

• Manufacturer Part Number: LPC47M112_07
• Description: Enhanced Super I/O Controller with LPC Interface
• Manufacturer: SMSC [SMSC Corporation]

Enhanced Super I/O Controller with LPC Interface
Datasheet
When RCVR FIFO and receiver interrupts are enabled, RCVR FIFO timeout interrupts occur as follows:
A. A FIFO timeout interrupt occurs if all the following conditions exist:
This will cause a maximum character received to interrupt issued delay of 160 msec at 300 BAUD with a 12 bit
character.
B. Character times are calculated by using the RCLK input for a clock signal (this makes the delay proportional to the
C. When a timeout interrupt has occurred it is cleared and the timer reset when the CPU reads one character from the
D. When a timeout interrupt has not occurred the timeout timer is reset after a new character is received or after the
When the XMIT FIFO and transmitter interrupts are enabled (FCR bit 0 = "1", IER bit 1 = "1"), XMIT interrupts occur as
follows:
A. The transmitter holding register interrupt (02H) occurs when the XMIT FIFO is empty; it is cleared as soon as the
B. The transmitter FIFO empty indications will be delayed 1 character time minus the last stop bit time whenever the
Character timeout and RCVR FIFO trigger level interrupts have the same priority as the current received data available
interrupt; XMIT FIFO empty has the same priority as the current transmitter holding register empty interrupt.
FIFO POLLED MODE OPERATION
With FCR bit 0 = "1" resetting IER bits 0, 1, 2 or 3 or all to zero puts the UART in the FIFO Polled Mode of operation.
Since the RCVR and XMITTER are controlled separately, either one or both can be in the polled mode of operation. In
this mode, the user's program will check RCVR and XMITTER status via the LSR. LSR definitions for the FIFO Polled
Mode are as follows:
Bit 0=1 as long as there is one byte in the RCVR FIFO.
Bits 1 to 4 specify which error(s) have occurred. Character error status is handled the same way as when in the
interrupt mode, the IIR is not affected since EIR bit 2=0.
Bit 5 indicates when the XMIT FIFO is empty.
Bit 6 indicates that both the XMIT FIFO and shift register are empty.
Bit 7 indicates whether there are any errors in the RCVR FIFO.
There is no trigger level reached or timeout condition indicated in the FIFO Polled Mode, however, the RCVR and XMIT
FIFOs are still fully capable of holding characters.
SMSC DS – LPC47M112
-
-
-
baudrate).
RCVR FIFO.
CPU reads the RCVR FIFO.
transmitter holding register is written to (1 of 16 characters may be written to the XMIT FIFO while servicing this
interrupt) or the IIR is read.
following occurs: THRE=1 and there have not been at least two bytes at the same time in the transmitter FIFO since
the last THRE=1. The transmitter interrupt after changing FCR0 will be immediate, if it is enabled.
BAUD RATE
DESIRED
134.5
At least one character is in the FIFO.
The most recent serial character received was longer than 4 continuous character times ago. (If 2 stop bits are
programmed, the second one is included in this time delay).
The most recent CPU read of the FIFO was longer than 4 continuous character times ago.
110
150
50
75
GENERATE 16X CLOCK
DIVISOR USED TO
2304
1536
1047
857
768
Table 30 - Baud Rates
DATASHEET
BETWEEN DESIRED AND ACTUAL
PERCENT ERROR DIFFERENCE
Page 70
0.001
0.004
-
-
-
1
SPEED BIT
HIGH
X
X
X
X
X
2
Rev. 02-16-07