LPC47M112_07 SMSC [SMSC Corporation], LPC47M112_07 Datasheet - Page 64

• Manufacturer Part Number: LPC47M112_07
• Description: Enhanced Super I/O Controller with LPC Interface
• Manufacturer: SMSC [SMSC Corporation]

Enhanced Super I/O Controller with LPC Interface
Datasheet
INTERRUPT IDENTIFICATION REGISTER (IIR)
Address Offset = 2H, DLAB = X, READ
By accessing this register, the host CPU can determine the highest priority interrupt and its source. Four levels of
priority interrupt exist. They are in descending order of priority:
1.
2.
3.
4.
Information indicating that a prioritized interrupt is pending and the source of that interrupt is stored in the Interrupt
Identification Register (refer to Interrupt Control Table). When the CPU accesses the IIR, the Serial Port freezes all
interrupts and indicates the highest priority pending interrupt to the CPU. During this CPU access, even if the Serial Port
records new interrupts, the current indication does not change until access is completed. The contents of the IIR are
described below.
Bit 0
This bit can be used in either a hardwired prioritized or polled environment to indicate whether an interrupt is pending.
When bit 0 is a logic "0", an interrupt is pending and the contents of the IIR may be used as a pointer to the appropriate
internal service routine. When bit 0 is a logic "1", no interrupt is pending.
Bits 1 and 2
These two bits of the IIR are used to identify the highest priority interrupt pending as indicated by the Interrupt Control
Table.
Bit 3
In non-FIFO mode, this bit is a logic "0". In FIFO mode this bit is set along with bit 2 when a timeout interrupt is pending.
Bits 4 and 5
These bits of the IIR are always logic "0".
Bits 6 and 7
These two bits are set when the FIFO CONTROL Register bit 0 equals 1.
SMSC DS – LPC47M112
Receiver Line Status (highest priority)
Received Data Ready
Transmitter Holding Register Empty
MODEM Status (lowest priority)
MODE
ONLY
BIT 3
FIFO
0
0
0
BIT 2
IDENTIFICATION
0
1
1
INTERRUPT
REGISTER
BIT 1
0
1
0
BIT 0
1
0
0
Bit 7
0
0
1
1
PRIORITY
Highest
Second
LEVEL
Table 29 - Interrupt Control
DATASHEET
Bit 6
-
0
1
0
1
INTERRUPT SET AND RESET FUNCTIONS
Trigger Level (BYTES)
None
Receiver
Status
Received Data
Available
INTERRUPT
Page 64
TYPE
RCVR FIFO
14
1
4
8
Line
None
Overrun Error,
Parity Error,
Framing Error or
Break Interrupt
Receiver Data
Available
INTERRUPT
SOURCE
Reading the Line
Status Register
Read Receiver
Buffer or the FIFO
INTERRUPT
CONTROL
RESET
-
Rev. 02-16-07