LPC47M112_07 SMSC [SMSC Corporation], LPC47M112_07 Datasheet - Page 202

• Manufacturer Part Number: LPC47M112_07
• Description: Enhanced Super I/O Controller with LPC Interface
• Manufacturer: SMSC [SMSC Corporation]

Enhanced Super I/O Controller with LPC Interface
Datasheet
33 APPENDIX - TEST MODE
33.1
Board Test Mode
Board test mode can be entered as follows:
On the rising (deasserting) edge of nPCI_RESET, drive nLFRAME low and drive LAD[0] low.
Exit board test mode as follows:
On the rising (deasserting) edge of nPCI_RESET, drive either nLFRAME or LAD[0] high.
See the “XNOR-Chain Test Mode” section below for a description of this board test mode.
XNOR-CHAIN TEST MODE
XNOR-Chain test structure allows users to confirm that all pins are in contact with the motherboard during assembly
and test operations. See Figure 39 below.
The XNOR-Chain test structure must be activated to perform these tests. When the XNOR-Chain is activated, the
LPC47M112 pin functions are disconnected from the device pins, which all become input pins except for one output
pin at the end of XNOR-Chain.
The tests that are performed when the XNOR-Chain test structure is activated require the board-level test hardware
to control the device pins and observe the results at the XNOR-Chain output pin.
The XNOR-Chain output pin is pin 52, GP31/FAN_TACH1. The nPCI_RESET pin and the power and ground pins are
not included in the XNOR-Chain. See the following subsections for more details.
I/O#3
I/O#1
I/O#2
XNor
I/O#n
Out
FIGURE 39 - XNOR-CHAIN TEST STRUCTURE
SMSC DS – LPC47M112
Page 202
Rev. 02-16-07
DATASHEET