XC68HC705F32 Motorola, XC68HC705F32 Datasheet - Page 100

• Manufacturer Part Number: XC68HC705F32
• Description: MICROCONTROLLER
• Manufacturer: Motorola

10
10.2
Four I/O pins located at port C (PC4 - PC7) are associated with the SPI data transfers. They are
the serial clock (SCK), the master in/slave out data line (MISO), the master out / slave in data line
(MOSI), and the active-low slave select (SS). When the SPI system is not utilized (SPE bit cleared
in the serial peripheral control register), the four pins (MISO, MOSI, SCK, and SS) are configured
as general-purpose I/O pins. The four SPI signals are discussed in the following paragraphs for
both master mode and slave mode of operation.
10.2.1
The MISO line is configured as an input, in a master device, and as an output in a slave device. It
is one of the two lines that transfer serial data in one direction. The MISO line of a slave device is
placed in the high-impedance state if the slave is not selected.
10.2.2
The MOSI line is configured as an output in a master device, and as an input in a slave device. It
is one of the two lines that transfer serial data in one direction.
10.2.3
The serial clock is used to synchronize data movement both in and out of the device through its
MOSI and MISO lines. The master and slave devices are capable of exchanging a byte of
information during a sequence of eight clock cycles. Since SCK is generated by the master device,
this line becomes an input on a slave device.
As shown in
and CPHA in the serial peripheral control register (SPCR). Both master and slave devices must
operate with the same timing. The master device always places data on the MOSI line a half cycle
before the clock edge (SCK), in order for the slave device to latch the data.
Two bits (SPR0 and SPR1) in the SPI control register (SPCR) of the master device select the clock
rate. In a slave device, SPR0 and SPR1 have no effect on the operation of the SPI.
MOTOROLA
10-2
Figure
SPI signal descriptions
Master in slave out (MISO)
Master out slave in (MOSI)
Serial clock (SCK)
10-1, four different timing relationships may be selected by control bits CPOL
SERIAL PERIPHERAL INTERFACE
MC68HC05F32
TPG