XC68HC705F32 Motorola, XC68HC705F32 Datasheet - Page 120

• Manufacturer Part Number: XC68HC705F32
• Description: MICROCONTROLLER
• Manufacturer: Motorola

11
RE — Receiver enable
When RE is clear (receiver disabled) all the status bits associated with the receiver (RDRF, IDLE,
OR, NF and FE) are inhibited. While the receiver is enabled, PC2 is forced to be an input.
RWU — Receiver wake-up
When the receiver wake-up bit is set by the user software, it puts the receiver to sleep and enables
the wake-up function. The type of wake-up mode for the receiver is determined by the WAKE bit
discussed above (in SCCR1). When the RWU bit is set, no status flags will be set. Flags which
were set previously will not be cleared when RWU is set.
If the WAKE bit is cleared, RWU is cleared by the SCI logic after receiving 10 (M = 0) or 11 (M =1)
consecutive ones. Under these conditions, RWU cannot be set if the line is idle. If the WAKE bit is
set, RWU is cleared after receiving an address bit. The RDRF flag will then be set and the address
byte stored in the receiver data register.
SBK — Send break
If the send break bit is toggled set and cleared, the transmitter sends 10 (M = 0) or 11 (M = 1) zeros
and then reverts to idle sending data. If SBK remains set, the transmitter will continually send
whole blocks of zeros (sets of 10 or 11) until cleared. At the completion of the break code, the
transmitter sends at least one high bit to guarantee recognition of a valid start bit. If the transmitter
is currently empty and idle, setting and clearing SBK is likely to queue two character times of break
because the first break transfers almost immediately to the shift register and the second is then
queued into the parallel transmit buffer.
11.11.4
The serial communications status register (SCSR) provides inputs to the interrupt logic circuits for
generation of the SCI system interrupt. In addition, a noise flag bit and a framing error bit are also
contained in the SCSR.
MOTOROLA
11-12
1 (set)
0 (clear) –
SCI status (SCSR)
Serial communications status register (SCSR)
–
Receiver enabled.
Receiver disabled.
SERIAL COMMUNICATIONS INTERFACE
Address
$004A TDRE
bit 7
TC
bit 6
RDRF IDLE
bit 5
bit 4
OR
bit 3
NF
bit 2
FE
bit 1
MC68HC05F32
0
bit 0
1100 0000
on reset
State
TPG