XC68HC705F32 Motorola, XC68HC705F32 Datasheet - Page 78

• Manufacturer Part Number: XC68HC705F32
• Description: MICROCONTROLLER
• Manufacturer: Motorola

7
7.3
The DMG has two registers (row frequency control register and column frequency control register)
for row and column frequency selection respectively, and one register (tone control register) for
tone output control and mode selection.
7.3.1
FCR4–FCR0 and FCC4–FCC0 control the frequency of the tone signals on the row and the
column paths respectively. The row and column paths are not exactly identical owing to the
presence of the high group pre-emphasis in the column path. In order to avoid the entry of the row
DTMF tone values to the column, and vice versa, the above cases are treated as illegal. The data
validator will disable all outputs when an illegal value is detected. The bit description for DTMF and
melody tone generation are shown in
responsibility to ensure good programming practice by initialising all registers to contain legal
values for the desired function.
7.3.2
This register controls the internal configuration and tone output timing of the DTMF/melody
generator.
MS1, MS0 — Melody select for operation
The MS0 and MS1 bits control the mode of operation of the DTMF/melody generator. There are
sine wave, square wave 1, square wave 2 and square wave 3 modes. They are specified as shown
in
MOTOROLA
7-4
Table
Column frequency control
Row frequency control
Tone control register
7-3.
register (FCR)
register (FCC)
(TNCR)
DMG registers
Row and column frequency control registers
Tone control register (TNCR)
Address
Address
Address
$000D
$000E
$000F
DTMF/MELODY GENERATOR
MS1
bit 7
bit 7
bit 7
0
0
MS0
bit 6
bit 6
bit 6
0
0
Table 7-1
TGER TGEC TNOE
bit 5
bit 5
bit 5
0
0
and
FCR4 FCR3 FCR2 FCR1 FCR0 undefined
FCC4 FCC3 FCC2 FCC1 FCC0 undefined
bit 4
bit 4
bit 4
Table 7-2
bit 3
bit 3
bit 3
0
bit 2
bit 2
bit 2
respectively. It is the user’s
0
bit 1
bit 1
bit 1
0
bit 0
bit 0
bit 0
MC68HC05F32
0000 0000
on reset
on reset
on reset
State
State
State
TPG