XC68HC705F32 Motorola, XC68HC705F32 Datasheet - Page 123

• Manufacturer Part Number: XC68HC705F32
• Description: MICROCONTROLLER
• Manufacturer: Motorola

SCP1, SCP0 — Serial prescaler select bits
These read/write bits determine the prescale factor by which the internal processor clock is divided
before it is applied to the transmitter and receiver rate control dividers. This common prescaled
output is used as the input to a divider that is controlled by the SCR0–SCR2 bits for the SCI
receiver and transmitter.
SCR2, SCR1, SCR0 — SCI rate select bits
These three read/write bits select the baud rates for the transmitter and the receiver. The prescaler
output is divided by the factors shown in
RCKB — SCI receive baud rate clock test
This bit is disabled and remains low in any mode other than test or bootstrap. Reset clears this bit.
While in test or bootstrap mode, this bit may be written but not read (reads always return a logic
zero). Setting this bit enables a baud rate counter test mode, where the exclusive-or of the receiver
clock (16 times the baud rate) is driven out of the PC3/TDO pin. This control bit is intended only
for factory testing of the MCU.
MC68HC05F32
SERIAL COMMUNICATIONS INTERFACE
SCR2
0
0
0
0
1
1
1
1
Table 11-3 Second prescaler stage
Table 11-2 First prescaler stage
SCP1
0
0
1
1
SCR1
0
0
1
1
0
0
1
1
Table
SCP0
0
1
0
1
SCR0
11-3.
0
1
0
1
0
1
0
1
division ratio (PRS1)
Prescaler
division ratio (PRS2)
13
1
3
4
Prescaler
128
16
32
64
1
2
4
8
MOTOROLA
11-15
TPG
11