XC68HC705F32 Motorola, XC68HC705F32 Datasheet - Page 69

• Manufacturer Part Number: XC68HC705F32
• Description: MICROCONTROLLER
• Manufacturer: Motorola

6.4
‘Output compare’ is a technique which may be used, for example, to generate an output waveform,
or to signal when a specific time period has elapsed, by presetting the output compare register to
the appropriate value.
There are two output compare registers: output compare register 1 (OCR1) and output compare
register 2 (OCR2).
There are two output compare interrupt enable bits (OC1IE and OC2IE).
6.4.1
The 16-bit output compare register 1 is made up of two 8-bit registers at locations $0022 (MSB)
and $0023 (LSB). The contents of the output compare register 1 are compared with the contents
of the free-running counter continually and, if a match is found, the corresponding output compare
flag (OC1F) in the timer status register is set. If the timer compare output enable bit (CO1E) is set,
the output level (OLVL1) is transferred to pin TCMP1. The output compare register 1 values and
the output level bit should be changed after each successful comparison to establish a new
elapsed timeout. An interrupt can also accompany a successful output compare provided the
corresponding interrupt enable bit (OC1IE) is set. (The free-running counter is updated every four
internal bus clock cycles.)
After a processor write cycle to the output compare register 1 containing the MSB ($0022), the
output compare function is inhibited until the LSB ($0023) is also written. The user must write both
bytes (locations) if the MSB is written first. A write made only to the LSB ($0023) will not inhibit the
compare 1 function. The processor can write to either byte of the output compare register 1 without
affecting the other byte. The output level (OLVL1) bit is clocked to the output level register and
hence to the TCMP1 pin whether the output compare flag 1 (OC1F) is set or clear. The minimum
time required to update the output compare register 1 is a function of the program rather than the
internal hardware. Because the output compare flag 1 and the output compare register 1 are not
defined at power on, and not affected by reset, care must be taken when initializing output compare
functions with software. The following procedure is recommended:
The purpose of this procedure is to prevent the OC1F bit from being set between the time it is read
and the write to the corresponding output compare register.
MC68HC05F32
Output compare 1 high (OCR1H)
Output compare 1 low (OCR1L)
– Write to output compare 1 high to inhibit further compares;
– Read the timer status register to clear OC1F (if set);
– Write to output compare 1 low to enable the output compare 1 function.
Output compare
Output compare register 1 (OCR1)
Address
$0022
$0023
16-BIT PROGRAMMABLE TIMER
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
MOTOROLA
Undefined
Undefined
on reset
State
TPG
6-11
6