XC68HC705F32 Motorola, XC68HC705F32 Datasheet - Page 106

• Manufacturer Part Number: XC68HC705F32
• Description: MICROCONTROLLER
• Manufacturer: Motorola

10
10.4.2
SPIF — SPI interrupt request flag
The serial peripheral data transfer flag bit is set after the eighth SCK cycle in a data transfer and
it is cleared by reading the SPSR register (with SPIF set) followed by reading from or writing to the
SPI data register (SPDAT).
WCOL — Write collision
The write collision bit is used to indicate that a serial transfer was in progress when the MCU tried
to write new data into the SPDAT data register. The MCU write is disabled to avoid writing over the
data being transmitted. No interrupt is generated because the error status flag can be read upon
completion of the transfer that was in progress at the time of the error. This flag is automatically
cleared by a read of the SPSR (with WCOL set) followed by an access (read or write) to the SPDAT
register.
MODF — SPI mode error interrupt status flag
This flag is set if the SS signal goes to its active-low level while the SPI is configured as a master
(MSTR = 1). This condition is not permitted in normal operation. This flag is automatically cleared
by a read of the SPSR (with MODF set) followed by a write to the SPCR register.
MOTOROLA
10-8
SPI status register (SPSR)
Status register (SPSR)
Address
SERIAL PERIPHERAL INTERFACE
$0045
Table 10-1 SPI rate selection
SPR1
SPIF WCOL
0
0
1
1
bit 7
bit 6
SPR0
0
1
0
1
bit 5
0
divided by
E clock
MODF
16
32
2
4
bit 4
0
bit 3
0
bit 2
0
bit 1
MC68HC05F32
0
bit 0
0000 0000
on reset
State
TPG