XC68HC705F32 Motorola, XC68HC705F32 Datasheet - Page 114

• Manufacturer Part Number: XC68HC705F32
• Description: MICROCONTROLLER
• Manufacturer: Motorola

11
11.7.1
In idle line wake-up mode, a dormant receiver wakes up as soon as the RDI line becomes idle. Idle
is defined as a continuous logic high level on the RDI line for ten (or eleven) full bit times. Systems
using this type of wake-up must provide at least one character time of idle between messages to
wake up sleeping receivers, but must not allow any idle time between characters within a message.
11.7.2
In address mark wake-up, the most significant bit (MSB) in a character is used to indicate whether
it is an address (1) or data (0) character. Sleeping receivers will wake up whenever an address
character is received. Systems using this method for wake-up would set the MSB of the first
character of each message and leave it clear for all other characters in the message. Idle periods
may be present within messages and no idle time is required between messages for this wake-up
method.
11.8
Receive data is the serial data that is applied through the input line and the SCI to the internal bus.
The receiver circuitry clocks the input at a rate equal to 16 times the baud rate. This time is referred
to as the RT rate in
The receiver clock generator is controlled by the baud rate register, as shown in
however, the SCI is synchronized by the start bit, independent of the transmitter.
Once a valid start bit is detected, the start bit, each data bit and the stop bit are sampled three
times at RT intervals 8 RT, 9 RT and 10 RT (1 RT is the position where the bit is expected to start),
as shown in
of the majority of the samples. A noise flag is set when all three samples on a valid start bit or data
bit or the stop bit do not agree
MOTOROLA
11-6
Figure
Idle line wake-up
Address mark wake-up
Receive data in (RDI)
Previous bit
RDI
11-4. The value of the bit is determined by voting logic which takes the value
Figure
Figure 11-4 SCI sampling technique used on all bits
16RT 1RT
SERIAL COMMUNICATIONS INTERFACE
11-5.
Present bit
.
8RT 9RT 10RT
Samples
16RT 1RT
Next bit
MC68HC05F32
Figure
11-1;
TPG