XC68HC705F32 Motorola, XC68HC705F32 Datasheet - Page 115

• Manufacturer Part Number: XC68HC705F32
• Description: MICROCONTROLLER
• Manufacturer: Motorola

11.9
When the input (idle) line is detected low, it is tested for three more sample times (referred to as
the start edge verification samples in
samples detect a logic zero, a valid start bit has been detected, otherwise the line is assumed to
be idle. A noise flag is set if one of the three verification samples detect a logic one, thus a valid
start bit could be assumed with a set noise flag present.
If there has been a framing error without detection of a break (10 zeros for 8 bit format or 11 zeros
for 9 bit format), the circuit continues to operate as if there actually was a stop bit, and the start
edge will be placed artificially. The last bit received in the data shift register is inverted to a logic
one, and the three logic one start qualifiers (shown in
register during the interval when detection of a start bit is anticipated (see
the start bit will be accepted no sooner than it is anticipated.
If the receiver detects that a break (RDRF = 1, FE = 1, receiver data register = $00) produced the
framing error, the start bit will not be artificially induced and the receiver must actually detect a logic
one before the start bit can be recognised (see
MC68HC05F32
RDI
RDI
RDI
16X internal sampling clock
RT clock edges for all three examples
Idle
1
1
1
Start bit detection
1
1
1
Figure 11-5 SCI examples of start bit sampling technique
1
1
1
1
1
1
SERIAL COMMUNICATIONS INTERFACE
1
1
1
Noise
1
1
0
1
1
1
1
1
1
Figure
1
1
1
qualifiers
Start
1
1
1
11-5). If at least two of these three verification
Figure
1
1
1
Start
Start
Start
1RT 2RT 3RT
0
0
0
Figure
11-7).
0
0
0
11-5) are forced into the sample shift
verification samples
4RT
Start edge
Noise
5RT
1
0
0
6RT
7RT
0
0
Figure
0
8RT
11-6); therefore,
MOTOROLA
TPG
11-7
11