XC68HC705F32 Motorola, XC68HC705F32 Datasheet - Page 68
XC68HC705F32
Manufacturer Part Number
XC68HC705F32
Description
MICROCONTROLLER
Manufacturer
Motorola
Datasheet
1.XC68HC705F32.pdf
(198 pages)
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6
6.3.2
The two 8-bit registers that make up the 16-bit input capture register 2 are read-only, and are used
to latch the value of the free-running counter after the input capture edge detector circuit 2 senses
a valid transition at pin TCAP2. When an input capture 2 occurs, the corresponding flag IC2F in
TSR is set. An interrupt can also accompany an input capture 2 provided the IC2IE bit in TCR1 is
set. The 8 most significant bits are stored in the input capture 2 high register at $0024, the 8 least
significant bits in the input capture 2 low register at $0025.
The result obtained from an input capture will be one greater than the value of the free-running
counter on the rising edge of the internal bus clock preceding the external transition. This delay is
required for internal synchronization. Resolution is one count of the free-running counter, which is
four internal bus clock cycles. The free-running counter contents are transferred to the input
capture register 2 on each valid signal transition whether the input capture 2 flag (IC2F) is set or
clear. The input capture register 2 always contains the free-running counter value that corresponds
to the most recent input capture 2. After a read of the input capture register 2 MSB ($0024), the
counter transfer is inhibited until the LSB ($0025) is also read. This characteristic causes the time
used in the input capture software routine and its interaction with the main program to determine
the minimum pulse period. A read of the input capture register 2 LSB ($0024) does not inhibit the
free-running counter transfer since the two actions occur on opposite edges of the internal bus
clock.
Reset does not affect the contents of the input capture register 2, except when exiting STOP mode
(see
MOTOROLA
6-10
Input capture 2 high (ICR2H)
Input capture 2 low (ICR2L)
Section
6.5).
Input capture register 2 (ICR2)
Address
$0024
$0025
16-BIT PROGRAMMABLE TIMER
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
MC68HC05F32
bit 0
Undefined
Undefined
on reset
State
TPG
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