XC68HC705F32 Motorola, XC68HC705F32 Datasheet - Page 107

• Manufacturer Part Number: XC68HC705F32
• Description: MICROCONTROLLER
• Manufacturer: Motorola

10.4.3
The serial peripheral data I/O register is used to transmit and receive data on the serial bus. Only
a write to this register will initiate transmission/reception of another byte, and this will only occur
in the master device. At the completion of transmitting a byte of data, the SPIF status bit is set in
both the master and slave devices.
When the user reads the serial peripheral data I/O register, a buffer is actually being read. The first
SPIF must be cleared by the time a second transfer of data from the shift register to the read buffer
is initiated or an overrun condition will exist. In cases of overrun, the byte which causes the overrun
is lost. A write to the serial peripheral data I/O register is not buffered and places data directly into
the shift register for transmission.
10.5
When the MCU enters wait mode, the CPU clock is halted. All CPU action is suspended; however,
the SPI system remains active. In fact an interrupt from the SPI causes the processor to exit the
wait mode.
10.6
When the MCU enters the stop mode, the internal oscillator is turned off, and the baud rate
generator which drives the SPI shuts down. This essentially stops all master mode SPI operation,
thus transfer is halted until the MCU exits the stop mode. If the stop mode is exited by a reset, then
the appropriate control/status bits are cleared and the SPI is disabled. If the device is in the slave
mode when the stop instruction is executed, the slave SPI will still operate. It can still accept data
and clock information in addition to transmitting its own data back to a master device.
At the end of a possible transmission with a slave SPI in the stop mode, no flags are set until the
MCU is “waked up” by an interrupt (IRQ, keyboard, LVI or CPI). Caution should be observed when
operating the SPI (as a slave) during the stop mode because none of the protection circuitry (write
collision, mode fault, etc.) is active.
MC68HC05F32
SPI data/IO register (SPDAT)
SPI data I/O register (SPDAT)
SPI during WAIT mode
SPI during STOP mode
Address
$0046
SERIAL PERIPHERAL INTERFACE
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
MOTOROLA
uuuu uuuu
on reset
State
TPG
10-9
10