XC68HC705F32 Motorola, XC68HC705F32 Datasheet - Page 139

• Manufacturer Part Number: XC68HC705F32
• Description: MICROCONTROLLER
• Manufacturer: Motorola

14.2.3.3
When configured as input pins, all eight port A lines provide a wired-OR keyboard interrupt facility
and will generate an interrupt, provided that the keyboard interrupt enable bit (KIE) in the
keyboard/timer register (KEY/TIM) is set. The address of the interrupt service routine is specified
by the contents of memory locations $0FFA and $0FFB. Since this interrupt vector is shared with
the IRQ external interrupt function the interrupt service routine should check KSF to determine the
interrupt source. KSF should be cleared by software in the interrupt service routine. Care must be
taken to allow adequate time for switch debounce before clearing the flag.
14.2.3.4
There is a low voltage interrupt flag that causes an interrupt whenever it is set and enabled. The
low voltage interrupt enable bit and the interrupt flag are located in the system option register
(SOR). This interrupt will vector to the service routine, located at the address specified by the
contents of memory locations $FFF4 and $FFF5.
14.2.3.5
An interrupt in the serial peripheral interface (SPI) occurs when one of the interrupt flag bits in the
SPI status register SPSR is set, provided the I-bit in the condition code register is clear and the
enable bit SPIE in the SPI control register is enabled. The SPI interrupt causes the program to
vector to memory location $FFF2 and $FFF3 which contains the starting address of the interrupt
service routine. Software in the SPI service routine must determine the priority and cause of the
SPI interrupt by examined the interrupt flag bits located in the SPI status register.
14.2.3.6
There are five different interrupt flags (TDRE, TC, OR, RDRE, IDLE) that will cause an SCI
interrupt whenever they are set and enabled. These five interrupt flags are found in the five most
significant bits of the SCI status register SCSR. The actual processor interrupt is generated only if
the I-bit in the condition code register is clear and the enable bit in the serial communication control
register 2 (SCCR2) is enabled. The SCI interrupt causes the program counter to vector to the
address pointed to by memory locations $FFF0–$FFF1 which contain the start address of the
interrupt service routine. Software in the SCI interrupt service routine must determine the priority
and cause of the SCI interrupt by examining the interrupt flags and the status bits in the serial
communications status register SCSR.
MC68HC05F32
Keyboard interrupt
Low voltage interrupt
Serial peripheral interface (SPI) interrupt
Serial communications interface (SCI) interrupt
RESETS AND INTERRUPTS
MOTOROLA
TPG
14-7
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