XC68HC705F32 Motorola, XC68HC705F32 Datasheet - Page 57

• Manufacturer Part Number: XC68HC705F32
• Description: MICROCONTROLLER
• Manufacturer: Motorola

5.3
The COP watchdog timer function is implemented by taking the output of the RTI circuit and further
dividing it by eight, as shown in
times the RTI period. This is because the COP will be cleared asynchronously with respect to the
value in the core timer counter register/RTI divider, hence the actual COP timeout period will vary
between 7x and 8x the RTI period. The minimum COP reset rates are shown in
The COP function is a mask option, enabled or disabled during device manufacture.
If the COP circuit times out, an internal reset is generated and the normal reset vector is fetched.
A COP timeout is prevented by writing a ‘0’ to bit 0 of address $FFF0. When the COP is cleared,
only the final divide-by-eight stage is cleared (see
5.4
The CPU clock halts during the WAIT mode, but the timer remains active. If the CTIMER interrupts
are enabled, then a CTIMER interrupt will cause the processor to exit the WAIT mode.
5.5
The timer is cleared when going into STOP mode. When STOP is exited by an external interrupt
or an external reset, the internal oscillator will restart, followed by an internal processor
stabilization delay (t
MC68HC05F32
Computer operating properly (COP) watchdog timer
Core timer during WAIT
Core timer during STOP
RT1
0
0
1
1
PORL
RT0
1
0
1
0
). The timer is then cleared and operation resumes.
16.384 kHz
Table 5-2 Minimum COP reset times
14 s
28 s
56 s
7 s
Figure
Minimum COP reset at f
447 kHz
513.8 ms
256.9 ms
5-1. Note that the minimum COP timeout period is seven
1.03 s
2.06 s
CORE TIMER
128.45 ms
895 kHz
256.9 ms
513.8 s
Figure
1.03 s
OP
frequency specified
5-1).
1.789 MHz
128.45 ms
64.19 ms
256.9 ms
513.8 ms
7 x RTI rate
7 x RTI rate
7 x RTI rate
7 x RTI rate
f
OP
Table
MOTOROLA
5-2.
TPG
5-5
5