XC68HC705F32 Motorola, XC68HC705F32 Datasheet - Page 59

• Manufacturer Part Number: XC68HC705F32
• Description: MICROCONTROLLER
• Manufacturer: Motorola

The MC68HC05F32 has two programmable 16-bit timers (TIMER1 and TIMER2), each with two
channels. The output compare function in TIMER2 has no external output, and is therefore used
for generating precision time intervals and interrupts only. The external connections are the only
differences between the two timers. The internal operation is identical (each timer has its own set
of registers), therefore only a complete description of TIMER1 is given.
The timer consists of a 16-bit read-only free-running counter, with a fixed divide-by-four prescaler,
plus the input capture/output compare circuitry. The timer can be used for many purposes including
measuring pulse length of two input signals and generating two output signals. Pulse lengths for
both input and output signals can vary from several microseconds to many seconds. The timer is
also capable of generating periodic interrupts or indicating passage of an arbitrary multiple of four
CPU cycles. A block diagram is shown in
Figure
The timer has a 16-bit architecture, hence each specific functional segment is represented by two
8-bit registers. These registers contain the high and low byte of that functional segment. Accessing
the low byte of a specific timer function allows full control of that function; however, an access of
the high byte inhibits that specific timer function until the low byte is also accessed.
The 16-bit programmable timer is monitored and controlled by a group of fifteen registers, full
details of which are contained in this section.
Note:
6.1
The key element in the programmable timer is a 16-bit, free-running counter or counter register,
preceded by a prescaler that divides the internal processor clock by four. The prescaler gives the
timer a resolution of 2 s if the internal bus clock is 2 MHz. The counter is incremented during the
low portion of the internal bus clock. Software can read the counter at any time without affecting
its value.
MC68HC05F32
6-3,
A problem may arise if an interrupt occurs in the time between the high and low bytes
being accessed. To prevent this, the I-bit in the condition code register (CCR) should be
set while manipulating both the high and low byte register of a specific timer function,
ensuring that an interrupt does not occur.
Figure 6-4
16-BIT PROGRAMMABLE TIMER
Counter
and
Figure
16-BIT PROGRAMMABLE TIMER
6-5.
Figure
6
6-1, and timing diagrams are shown in
MOTOROLA
Figure
TPG
6-2,
6-1
6