XC68HC705F32 Motorola, XC68HC705F32 Datasheet - Page 22
XC68HC705F32
Manufacturer Part Number
XC68HC705F32
Description
MICROCONTROLLER
Manufacturer
Motorola
Datasheet
1.XC68HC705F32.pdf
(198 pages)
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MOTOROLA
1-2
Fully static design featuring the industry-standard M68HC05 CPU core
32512 bytes of user ROM, plus 16 bytes for vectors
240 bytes of bootloader ROM
920 bytes of RAM plus 20 bytes of LCD RAM
256 bytes of user EEPROM
DTMF/melody generator
16-bit programmable timer with four input captures and four output compares (the outputs of
two of the output compares are used internally and do not have external connections)
15 stage multipurpose core timer with timer overflow, real time interrupt and COP watchdog
LCD driver with 4 backplanes and 40 frontplanes
8-channel, 8-bit analog-to-digital (A/D) converter
Power saving STOP and WAIT modes
I/O lines
Keyboard interrupt facility on eight of the I/O lines, with high or low voltage level interrupt
triggers
Hardware interrupt with edge or edge-and-level sensitive interrupt trigger
SCI and SPI subsystems
On-chip oscillators
Three PWM channels
Two selectable bus frequencies
32kHz independent clock system
Power-on and power-off resets; low voltage detection circuitry (EEPROM)
Available in 100-pin QFP and 80-pin QFP
– 100 QFP configuration – total of 80 I/O pins configured as:
– 80 QFP configuration – total of 69 I/O pins configured as:
16 dedicated bidirectional I/O
64 shared with peripherals
16 dedicated bidirectional I/O
53 shared with peripherals
The 80-pin version is only a bond option. Pins PE4, PD7–PD0, PC4, PC5 are shared
with module functions which cannot work on the 80-pin package. These modules and
their corresponding pin functions should not be enabled.
Features
INTRODUCTION
MC68HC05F32
TPG
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