XC68HC705F32 Motorola, XC68HC705F32 Datasheet - Page 28

• Manufacturer Part Number: XC68HC705F32
• Description: MICROCONTROLLER
• Manufacturer: Motorola

2
2.3
The MC68HC05F32 MCU contains a System Option Register which is located at address $4D.
This register is used to control the LVI and the clock system.
LVIF, LVIE, LVION — Low voltage interrupt bits
The LVIF flag is set by the low voltage detection circuit, if the LVI is enabled and power supply VDD
falls below V
The low voltage interrupt must be enabled by first setting bit LVION Low Voltage Interrupt On and
after that setting bit LVIE Low Voltage Interrupt Enable. After power on reset the LVI circuit is
disabled.
SC — System clock option
After power on reset the internal bus frequency is f=3.58Mhz/2. If the bit SC System Clock is set
the system speed is reduced to f=3.58Mhz/4, with the exception of the DTMF generator (Oscillator
Frequency 3.58Mhz).
IRQ — Interrupt sensitivity
IRQ edge or level sensitivity
KEYMUX — Multiplex bit for access of interrupt flag
The KEYMUX bit switches between the port A data register and the interrupt status register
IRSTATE, that both have the address $0000. If KEYMUX is cleared normal read and write access
to port A is possible. If KEYMUX is set, a read or write operation at address $0000 accesses the
8 interrupt status flags.
KEYCLR — Keyboard interrupt clear
The keyboard wake-up interrupt status flag (Bit 7, $1B) is cleared by writing a “1” to bit KEYCLR.
A read access to this bit always returns “0”.
PUEN — PORTC pull-up enable
After power on reset the pull-up resistors in port C are disabled. If bit PUEN is set, the pull-up
resistors in port C are enabled. Writing a “0” to PUEN disables the pull-up function.
MOTOROLA
2-4
System options register (SOR)
1 (set)
0 (clear) –
lvi
.
System options register (SOR)
–
MODES OF OPERATION AND PIN DESCRIPTIONS
IRQ input edge and level sensitive
IRQ input edge sensitive
Address
$004D
LVIF
bit 7
LVIE
bit 6
LVION
bit 5
SC
bit 4
IRQ KEYMUXKEYCLR PUEN 0000 0000
bit 3
bit 2
bit 1
MC68HC05F32
bit 0
on reset
State
TPG