XC68HC705F32 Motorola, XC68HC705F32 Datasheet - Page 25
XC68HC705F32
Manufacturer Part Number
XC68HC705F32
Description
MICROCONTROLLER
Manufacturer
Motorola
Datasheet
1.XC68HC705F32.pdf
(198 pages)
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The normal operating mode of the MC68HC05F32 is single chip mode. There is also a bootloader
mode, primarily for factory test purposes. In addition to these modes, there are three low power
modes which may be entered and exited at will from user mode: STOP, WAIT and data retention.
2.1
This is the normal user operating mode, in which the device functions as a self-contained
microcomputer unit, with all on-board peripherals and I/O ports available to the user. All address
and data activity occurs within the MCU.
2.2
2.2.1
The STOP instruction places the MCU in its lowest power consumption mode. In STOP mode, the
internal oscillator is turned off, halting all internal processing, including timer (and COP watchdog
timer) operation, 16-bit timers, SPI, SCI, PWM and A/D converter.
During STOP mode, the core timer interrupt flags (CTOF and RTIF) and interrupt enable bits
(TOFE and RTIE) in the CTCSR as well as the 16-bit timer flags in register TSR and interrupt
enable bits in register TCR are cleared by internal hardware. The I-bit in the CCR is cleared to
enable external interrupts. All other registers, the remaining bits in the CTCSR, and memory
contents remain unaltered. All input/output lines remain unchanged. The processor can be
brought out of STOP mode only by an interrupt (IRQ, Keyboard, LVI or CPI from the 32 kHz clock
system) if enabled or RESET (external reset or low voltage reset – LVR). See
The STOP instruction can be disables by a mask option. When disabled, the STOP instruction is
executed as a NOP.
MC68HC05F32
MODES OF OPERATION AND PIN
Single-chip mode
Low power modes
STOP mode
MODES OF OPERATION AND PIN DESCRIPTIONS
DESCRIPTIONS
2
Figure
MOTOROLA
2-1.
TPG
2-1
2
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