XC68HC705F32 Motorola, XC68HC705F32 Datasheet - Page 140

• Manufacturer Part Number: XC68HC705F32
• Description: MICROCONTROLLER
• Manufacturer: Motorola

14
14.2.3.7
There is a timer interrupt flag that causes a CPI interrupt from the 32 kHz clock system whenever
set and enabled. The interrupt flag and enable bits are located in the CPI control and status
register (CPICSR). An interrupt will vector to the same interrupt service routine as the core timer
interrupts, located at the address specified by the contents of memory location $FFF8 and $FFF9.
14.2.4
The following three functions (RESET, STOP, and WAIT) are not in the strictest sense interrupts.
However, they are acted upon in a similar manner. Flowcharts for STOP and WAIT are shown in
Figure
RESET: A reset condition causes the program to vector to its starting address, which is contained
in memory locations $FFFE (MSB) and $FFFF (LSB). The I-bit in the condition code register is
also set, to disable interrupts.
STOP: The STOP instruction causes the oscillator to be turned off and the processor to ‘sleep’ until
an external interrupt (IRQ), a low voltage interrupt (LVI), a custom periodic interrupt (CPI), or a
keyboard interrupt occurs, or the device is reset.
WAIT: The WAIT instruction causes all processor clocks to stop, but leaves the timer clocks
running. This ‘rest’ state of the processor can be cleared by reset, an external interrupt (IRQ), a
keyboard interrupt, a timer interrupt (core or 16-bit), or a CPI, SPI, SCI, LVI interrupt. There are no
special WAIT vectors for these interrupts.
MOTOROLA
14-8
2-1.
Custom periodic interrupt (CPI)
Hardware controlled interrupt sequence
RESETS AND INTERRUPTS
MC68HC05F32
TPG