XC68HC705F32 Motorola, XC68HC705F32 Datasheet - Page 191

• Manufacturer Part Number: XC68HC705F32
• Description: MICROCONTROLLER
• Manufacturer: Motorola

RESET 2–5
resets 14–1
RFQ1, RFQ0 bits in CPICSR 13–2
RIE bit in SCCR2 11–11
RT1, RT0 bits in CTCSR 5–4
RTIE bit in CTCSR 5–3
RTIF bit in CTCSR 5–3
RWU bit in SCCR2 11–12
S
SBK bit in SCCR2 11–12
SC bit in SOR 2–4
SCCR1 — serial communications control register 1 11–9
SCCR2 — serial communications control register 2 11–11
SCDR — serial communications data register 11–9
SCI
SCK 2–6
SCP1, SCP0 bits in BAUD 11–15
SCSR — serial communications status register 11–12
SCT2, SCT1, SCT0 bits in BAUD 11–15
SOR 2–4
SP – stack pointer 15–2
MC68HC05F32
COP 14–2
illegal address 14–1
power-on reset 14–1
RESET pin 2–5
CPOL – clock polarity bit 11–11
M – mode (select character format) 11–10
R8 – receive data bit 8 11–10
T8 – transmit data bit 8 11–10
WAKE – wake-up mode select bit 11–10
ILIE – idle line interrupt enable 11–11
RE – receiver enable 11–12
RIE – receiver interrupt enable 11–11
RWU – receiver wake-up 11–12
SBK – send break 11–12
TCIE – transmit complete interrupt enable 11–11
TE – transmitter enable 11–11
TIE – transmit interrupt enable 11–11
baud rate selection 11–16
block diagram 11–2
data format 11–5
receiver wake-up 11–5
start bit detection 11–7
FE – framing error flag 11–14
IDLE – idle line detected flag 11–13
NF – noise error flag 11–14
OR – overrun error flag 11–13
RDRF – receive data register full flag 11–13
TC – transmit complete flag 11–13
TDRE – transmit data register empty flag 11–13
IRQ — interrupt sensitivity 2–4
KEYCLR — keyboard interrupt clear 2–4
KEYMUX — multiplex bit for access of interrupt flag
LVIF, LVIE, LVION — low voltage interrupt bits 2–4
PUEN — PORTC pull-up enable 2–4
SC — system clock option 2–4
2–4
,
14–1
INDEX
SPCR
SPI 10–9
SPI registers
SPI signal descriptions
SPIE 10–6
SPSR
SS 2–6
STOP mode 2–1
successive approximation (SAR) - see A/D converter
SWI – see interrupts
system options register 2–4
T
T8 bit in SCCR1 11–10
TC bit in SCSR 11–13
TCAP1 2–6
TCAP1, TCAP2 bits in TSR 6–8
TCAP2 2–6
TCAP3 2–6
TCAP4 2–6
TCIE bit in SCCR2 11–11
TCMP1 2–6
TCMP2 2–6
TCR1 — timer control register 1 6–4
TCR2 — timer control register 2 6–4
CPHA – clock phase 10–7
CPOL – clock polarity 10–7
DOD – direction of data 10–7
MSTR – master/slave mode select 10–7
SPE – SPI system enable 10–7
SPIE – SPI interrupt enable 10–6
SPR1, SPR0 – SPI clock select bits 10–7
block diagram 10–5
during STOP mode 10–9
during WAIT mode 10–9
features 10–1
rate selection 10–8
registers 10–6
SPCR — SPI control register 10–6
SPDAT — SPI data I/O register 10–9
SPSR — SPI status register 10–8
master in slave out (MISO) 10–2
master out slave in (MOSI) 10–2
serial clock (SCK) 10–2
slave select (SS) 10–4
MODF – SPI mode error interrupt status flag 10–8
SPIF – SPI interrupt request flag 10–8
WCOL – write collision 10–8
CO1E – compare output enable bit 1 6–5
IC1IE – input capture interrupt enable 1 6–5
IC2IE – input capture interrupt enable 2 6–5
IEDG1 – input edge bit 1 6–5
IEDG2 – input edge bit 2 6–6
OC1IE – output compare interrupt enable 1 6–5
OLVL1 – output level bit 1 6–6
TOIE – timer overflow interrupt enable 6–5
CO2E – compare output enable bit 2 6–6
OC2IE – output compare interrupt enable 2 6–6
MOTOROLA
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