XC68HC705F32 Motorola, XC68HC705F32 Datasheet - Page 55

• Manufacturer Part Number: XC68HC705F32
• Description: MICROCONTROLLER
• Manufacturer: Motorola

5.2
5.2.1
CTOF — Core timer overflow
CTOF is a read-only status bit and is set when the core timer counter register rolls over from $FF
to $00; an interrupt request will be generated if CTOFE is set. When set, CTOF may be cleared by
writing a ‘1’ to RTOF.
RTIF — Real time interrupt flag
RTIF is a read-only status bit and is set when the output of the chosen stage becomes active; an
interrupt request will be generated if RTIE is set. When set, the bit may be cleared by writing a ‘1’
to RRTIF. Reset also clears this bit.
CTOFE — Core timer overflow enable
Setting this bit enables the core timer overflow Interrupt. A CPU interrupt request will then be
generated whenever the CTOF bit becomes set and the I-bit in the CCR is clear. Clearing this bit
disables the core timer overflow interrupt capability.
RTIE — Real time interrupt enable
Setting this bit enables the real time interrupt. A CPU interrupt request will then be generated
whenever the RTIF bit becomes set and the I-bit in the CCR is clear. Clearing this bit disables the
real time interrupt capability.
MC68HC05F32
Core timer control/status (CTCSR)
1 (set)
0 (clear) –
1 (set)
0 (clear) –
1 (set)
0 (clear) –
1 (set)
0 (clear) –
Core timer registers
Core timer control and status register (CTCSR)
–
–
–
–
Core timer overflow has occurred.
No core timer overflow interrupt has been generated.
A real time interrupt has occurred.
No real time interrupt has been generated.
Core timer overflow interrupt is enabled.
Core timer overflow interrupt is disabled.
Real time interrupt is enabled.
Real time interrupt is disabled.
Address
$0008
CTOF
bit 7
CORE TIMER
RTIF CTOFE RTIE
bit 6
bit 5
bit 4
RTOF RRTIF
bit 3
bit 2
RT1
bit 1
RT0
bit 0
MOTOROLA
0000 0011
on reset
State
TPG
5-3
5