XC68HC705F32 Motorola, XC68HC705F32 Datasheet - Page 136

• Manufacturer Part Number: XC68HC705F32
• Description: MICROCONTROLLER
• Manufacturer: Motorola

14
14.2.1
Each potential interrupt source is assigned a priority which means that if more than one interrupt
is pending at the same time, the processor will service the one with the highest priority first. For
example, if both an external interrupt and a timer interrupt are pending after an instruction
execution, the external interrupt is serviced first.
14.2.2
The software interrupt (SWI) is an executable instruction and a nonmaskable interrupt: it is
executed regardless of the state of the I-bit in the CCR. If the I-bit is zero (interrupts enabled), SWI
is executed after interrupts that were pending when the SWI was fetched, but before interrupts
generated after the SWI was fetched. The SWI interrupt service routine address is specified by the
contents of memory locations $FFFC and $FFFD.
14.2.3
If the interrupt mask bit (I-bit) of the CCR is set, all maskable interrupts (internal and external) are
masked. Clearing the I-bit allows interrupt processing to occur. IRQ is software selectable as either
edge or edge-and-level sensitive (bit 3 of the system option register).
Note:
14.2.3.1
There are two different core timer interrupt flags that cause a CTIMER interrupt whenever an
interrupt is enabled and its flag becomes set, namely RTIF and CTOF. The interrupt flags and
enable bits are located in the CTIMER control and status register (CTCSR). These interrupts will
vector to the same interrupt service routine, whose start address is contained in memory locations
$FFF8 and $FFF9 (see
To make use of the real time interrupt the RTIE bit must first be set. The RTIF bit will then be set
after the specified number of counts.
To make use of the core timer overflow interrupt, the CTOFE bit must first be set. The CTOF bit will
then be set when the core timer counter register overflows from $FF to $00.
MOTOROLA
14-4
The internal interrupt latch is cleared in the first part of the interrupt service routine;
therefore, one external interrupt pulse could be latched and serviced as soon as the I-bit
is cleared.
Interrupt priorities
Non-maskable software interrupt (SWI)
Maskable hardware interrupts
Real time and core timer (CTIMER) interrupts
Section 5.2.1
RESETS AND INTERRUPTS
and
Figure
5-1).
MC68HC05F32
TPG