XC68HC705F32 Motorola, XC68HC705F32 Datasheet - Page 131

• Manufacturer Part Number: XC68HC705F32
• Description: MICROCONTROLLER
• Manufacturer: Motorola

13
32 KHZ CLOCK SYSTEM
13.1
32 kHz clock system
The 32 kHz clock system is mostly independent from the rest of the MCU. WAIT mode and STOP
mode do not affect the work of the 32 kHz clock system. For the reason of power saving the
oscillator and the divider can be stopped if the oscillator input pin OSC3 is held on fixed potential.
The 32 kHz clock system is provided to generate a refresh signal at port E pin 4 and an custom
periodic interrupt (CPI) with a period of 0.5s. The refresh frequency and the periodic interrupt are
under the control of the custom periodic interrupt control/status register located at $4C.
13.1.1
Custom periodic interrupt control/status register (CPICSR)
The CPICSR contains the interrupt flag CPIF, the interrupt enable bit CPIE and refresh frequency
select bits RFQ1, RFQ0.
State
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
on reset
13
CPI control/status (CPICSR)
$004C
0
CPIF
0
CPIE
0
0
RFQ1 RFQ0 0000 0000
CPIF — Custom periodic interrupt flag
CPIF is a clearable, read-only status bit and is set when the 14-bit counter changes from $3FFF
to $0000. A CPU interrupt request will be generated if CPIE is set. Clearing the CPIF is done by
writing a ‘0’ to it. Writing a ‘1’ to CPIF has no effect on the bit’s value. Reset clears CPIF.
CPIE — Custom periodic interrupt enable
When this bit is cleared, the CPI interrupts are disabled. When this bit is set, a CPU interrupt
request is generated when the CPIF bit is set. Reset clears this bit.
TPG
MC68HC05F32
32 KHZ CLOCK SYSTEM
MOTOROLA
13-1