XC68HC705F32 Motorola, XC68HC705F32 Datasheet - Page 26

• Manufacturer Part Number: XC68HC705F32
• Description: MICROCONTROLLER
• Manufacturer: Motorola

2
2.2.2
The WAIT instruction places the MCU in a low power consumption mode, though it consumes
more power than in STOP mode. All CPU action is suspended, but the Core timer, the first 16-bit
timer (TCAP1, 2 and TCMP1, 2), the DMG and the LCD remain active. If bit 7 (WTLCDO) of the
LCD control register, $1E, is reset, the SPI, the SCI, the second 16-bit timer (TCAP3, 4 and
TCMP3, 4) and the A/D converter, also remain active in WAIT mode. If, however, WTLCDO is set
they are turned off.
An interrupt from the core timer, 16-bit timers, SPI, SCI, IRQ, keyboard, LVI, OR CPI from the 32
kHz clock system, if enabled, will cause the MCU to exit the WAIT mode. An external reset, or LVR,
causes the MCU to exit the wait mode.
During WAIT mode, the I-bit in the CCR is cleared to enable interrupts. All other registers, memory
and input/output lines remain in their previous state. See
2.2.3
The contents of the RAM and CPU registers are retained at supply voltages as low as 2.0Vdc.
This is called the data retention mode, in which data is maintained but the device is not guaranteed
to operate. If the voltage drops below V
For lowest power consumption in data retention mode the device should be put into STOP mode
before reducing the supply voltage, to ensure that all the clocks are stopped. If the device is not
in STOP mode then it is recommended that RESET be held low whilst the power supply is outwith
the normal operating range, to ensure that processing is suspended in an orderly manner.
Recovery from data retention mode, after the power supply has been restored, is by an external
interrupt, or by pulling the RESET line high.
MOTOROLA
2-2
WAIT mode
Data retention mode
MODES OF OPERATION AND PIN DESCRIPTIONS
ROFF
the low voltage reset circuit generates a reset.
Figure
2-1.
MC68HC05F32
TPG