XC68HC705F32 Motorola, XC68HC705F32 Datasheet - Page 132

• Manufacturer Part Number: XC68HC705F32
• Description: MICROCONTROLLER
• Manufacturer: Motorola

13
RFQ1–RFQ0 — Refresh frequency select
These two read/write bits select one of four taps from the 14-stage counter to provide a refresh
clock with a frequency according to
frequency.
13.1.1.1
If bit 4 in the control register of port E is set, the output of the 32 kHz clock system is connected
to the pin PE4/REFRESH. The refresh clock rate is under software control and is specified in
Table
13.2
Stop mode does not affect the work of the 32 kHz clock system. If the CPI interrupt is enabled, a
custom periodic interrupt will cause the processor to wake up from the STOP mode.
13.3
The CPU clock halts during the WAIT mode, but the 32 kHz clock system remains active. If the
CPI interrupt is enabled, a custom periodic interrupt will cause the processor to exit the WAIT
mode.
MOTOROLA
13-2
13-1.
Refresh clock
Operation during STOP mode
Operation during WAIT mode
Table 13-1 Refresh clock (32.768 kHz crystal)
RFQ1
0
0
1
1
32 KHZ CLOCK SYSTEM
RFQ0
Table
0
1
0
1
13-1. Reset clears these bits, selecting the highest
Refresh clock frequency
8.192 kHz (reset condition)
4.096 kHz
2.048 kHz
1.024 kHz
MC68HC05F32
TPG