XC68HC705F32 Motorola, XC68HC705F32 Datasheet - Page 135

• Manufacturer Part Number: XC68HC705F32
• Description: MICROCONTROLLER
• Manufacturer: Motorola

14.2
The MCU can be interrupted by nine different sources, eight maskable hardware interrupts and
one nonmaskable software interrupt:
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Interrupts cause the processor to save the register contents on the stack and to set the interrupt
mask (I-bit) to prevent additional interrupts. The RTI instruction (return from interrupt) causes the
register contents to be recovered from the stack and normal processing to resume. While
executing the RTI instruction, the interrupt mask bit (I-bit) will be cleared providing the
corresponding enable bit stored on the stack is zero, i.e. the interrupt is disabled.
Unlike reset, hardware interrupts do not cause the current instruction execution to be halted, but
are considered pending until the current instruction is complete. The current instruction is the one
already fetched and being operated on. When the current instruction is complete, the processor
checks all pending hardware interrupts. If interrupts are not masked (CCR I-bit clear) and the
corresponding interrupt enable bit is set, the processor proceeds with interrupt processing;
otherwise, the next instruction is fetched and executed.
flow.
Note:
MC68HC05F32
External signal on the IRQ pin; IRQ is mask selectable as edge or edge-and-level sensitive
Keyboard interrupt
Core timer interrupt
16-bit programmable timer interrupt
Low voltage interrupt (LVI) – EEPROM
Serial peripheral interface (SPI) interrupt
Serial communications interface (SCI) interrupt
32 kHz clock system interrupt
Software interrupt instruction (SWI)
Power-on or external reset clears all interrupt enable bits thus preventing interrupts
during the reset sequence.
Interrupts
RESETS AND INTERRUPTS
Figure 14-1
shows the interrupt processing
MOTOROLA
TPG
14-3
14