XC68HC705F32 Motorola, XC68HC705F32 Datasheet - Page 93

• Manufacturer Part Number: XC68HC705F32
• Description: MICROCONTROLLER
• Manufacturer: Motorola

9
A/D CONVERTER
The analog to digital converter system consists of a 12-channel, multiplexed input to a successive
approximation A/D converter. Eight of the A/D input channels are connected to pins PD0–PD7 and
the particular input to be selected is determined by the setting/clearing of the CHx bits in the A/D
status/control register at $4F. A further four channels are available internally for test purposes. In
addition to the A/D status/control register (ADSCR) there is one 8-bit result data register at
address $4E.
The A/D converter is ratiometric and a dedicated pin, VREFH, is used to supply the upper
reference voltage level of each analog input. The lower voltage reference point, V
, is internally
REFL
connected to the AVSS pin. An input voltage equal to or greater than V
converts to $FF (full
9
RH
scale) with no overflow indication. For ratiometric conversions, the source of each analog input
should use V
as the supply voltage and be referenced to AV
.
REFH
SS
The A/D converter can operate from either the bus clock or an internal RC type oscillator. The
internal RC type oscillator is activated by the ADRC bit in the A/D status/control register (ADRC)
and can be used to give a sufficiently high clock rate to the A/D converter when the bus speed is
too low to provide accurate results (see
Section
9.2.1). When the A/D converter is not being used
it can be disconnected using the ADON bit in the ADSCR register, in order to save power (see
Section
9.2.1).
9.1
A/D converter operation
The A/D converter consists of an analog multiplexer, an 8-bit digital-to-analog capacitor array, a
comparator and a successive approximation register (SAR). See
Figure
9-1.
The A/D reference inputs is applied to a precision internal digital-to-analog converter. Control logic
drives this D/A converter and the analog output is successively compared with the analog input
sampled at the beginning of the conversion. The conversion is monotonic with no missing codes.
The result of each successive comparison is stored in the SAR and, when the conversion is
complete, the contents of the SAR are transferred to the read-only result data register ($4E), and
the conversion complete flag, COCO, is set in the A/D status/control register ($4F).
TPG
MC68HC05F32
A/D CONVERTER
MOTOROLA
9-1