XC68HC705F32 Motorola, XC68HC705F32 Datasheet - Page 61

• Manufacturer Part Number: XC68HC705F32
• Description: MICROCONTROLLER
• Manufacturer: Motorola

6.1.1
The double-byte, free-running counter can be read from either of two locations, $0028 – $0029
(counter register) or $002A – $002B (counter alternate register). A read from only the less
significant byte (LSB) of the free-running counter ($0029 or $002B) receives the count value at the
time of the read. If a read of the free-running counter or alternate counter register first addresses
the more significant byte (MSB) ($0028 or $002A), the LSB is transferred to a buffer. This buffer
value remains fixed after the first MSB read, even if the user reads the MSB several times. This
buffer is accessed when reading the free-running counter or alternate counter register LSB and
thus completes a read sequence of the total counter value. In reading either the free-running
counter or alternate counter register, if the MSB is read, the LSB must also be read to complete
the sequence. If the timer overflow flag (TOF) is set when the counter register LSB is read then a
read of the timer status register (TSR) will clear the flag.
The counter alternate register differs from the counter register only in that a read of the LSB does
not clear TOF. Therefore, where it is critical to avoid the possibility of missing timer overflow
interrupts due to clearing of TOF, the alternate counter register should be used.
The free-running counter is set to $FFFC during power-on and external reset and is always a
read-only register. During a power-on reset, the counter begins running after the oscillator start-up
delay. Because the free-running counter is 16 bits preceded by a fixed divide-by-4 prescaler, the
value in the free-running counter repeats every 262,144 internal bus clock cycles. TOF is set when
the counter overflows (from $FFFF to $0000); this will cause an interrupt if TOIE is set.
The divide-by-4 prescaler is also reset and the counter resumes normal counting operation. All of
the flags and enable bits remain unaltered by this operation. If access has previously been made
to the high byte of the free-running counter ($0028 or $002A), then the reset counter operation
terminates the access sequence.
Caution: This operation may affect the function of the watchdog system (see
MC68HC05F32
Alternate counter high (ACNTH)
Alternate counter low (ACNTL)
Timer counter high (CNTH)
Timer counter low (CNTL)
Counter register and alternate counter register
Address
Address
$002A
$0028
$0029
$002B
16-BIT PROGRAMMABLE TIMER
bit 7
bit 7
bit 6
bit 6
bit 5
bit 5
bit 4
bit 4
bit 3
bit 3
bit 2
bit 2
bit 1
bit 1
Section
bit 0
bit 0
MOTOROLA
5.3).
1111 1111
1111 1100
1111 1111
1111 1100
on reset
on reset
State
State
TPG
6-3
6