XC68HC705F32 Motorola, XC68HC705F32 Datasheet - Page 64

• Manufacturer Part Number: XC68HC705F32
• Description: MICROCONTROLLER
• Manufacturer: Motorola

6
IEDG2 — Input edge 2
When IEDG2 is set, a positive-going edge on the TCAP2 pin will trigger a transfer of the
free-running counter value to the input capture register 2. When clear, a negative-going edge
triggers the transfer.
OLVL1 — Output level 1
When OLV1 is set a high output level will be clocked into the output level register by the next
successful output compare, and will appear on the TCMP1 pin. When clear, it will be a low level
which will appear on the TCMP1 pin.
OC2IE — Output compare 2 interrupt enable
register) is set.
CO2E — Timer compare 2 output enable
If this bit is set, the output from timer output compare 2 is enabled.
OLVL2 — Output level 2
When OLV2 is set a high output level will be clocked into the output level register by the next
successful output compare, and will appear on the TCMP2 pin. When clear, it will be a low level
which will appear on the TCMP2 pin.
MOTOROLA
6-6
If this bit is set, a timer interrupt is enabled whenever the OC2F status flag (in the timer status
1 (set)
0 (clear) –
1 (set)
0 (clear) –
1 (set)
0 (clear) –
1 (set)
0 (clear) –
1 (set)
0 (clear) –
–
–
–
–
–
TCAP2 is positive-going edge sensitive.
TCAP2 is negative-going edge sensitive.
A high output level will appear on the TCMP1 pin.
A low output level will appear on the TCMP1 pin.
Interrupt enabled.
Interrupt disabled.
Output compare 2 enabled.
Output compare 2 disabled.
A high output level will appear on the TCMP2 pin.
A low output level will appear on the TCMP2 pin.
16-BIT PROGRAMMABLE TIMER
MC68HC05F32
TPG