MC9S12XDT256CAA Freescale Semiconductor, MC9S12XDT256CAA Datasheet - Page 1077
MC9S12XDT256CAA
Manufacturer Part Number
MC9S12XDT256CAA
Description
IC MCU 256K FLASH 80-QFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.MC9S12XD64CAA.pdf
(1348 pages)
Specifications of MC9S12XDT256CAA
Core Processor
HCS12X
Core Size
16-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
59
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
80-QFP
Processor Series
S12XD
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
16 KB
Interface Type
CAN/I2C/SCI/SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
59
Number Of Timers
12
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
EVB9S12XDP512E
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S12XDT256CAA
Manufacturer:
Freescale Semiconductor
Quantity:
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Part Number:
MC9S12XDT256CAAR
Manufacturer:
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All bits in the ECLKDIV register are readable, bits 6–0 are write once and bit 7 is not writable.
26.3.2.2
This register is reserved for factory testing and is not accessible.
All bits read 0 and are not writable.
26.3.2.3
This register is reserved for factory testing and is not accessible.
Freescale Semiconductor
EDIV[5:0]
EDIVLD
PRDIV8
Reset
Reset
Field
5–0
7
6
W
W
R
R
EDIVLD
Clock Divider Loaded
0 Register has not been written.
1 Register has been written to since the last reset.
0 The oscillator clock is directly fed into the ECLKDIV divider.
1 Enables a Prescalar by 8, to divide the oscillator clock before feeding into the clock divider.
Clock Divider Bits — The combination of PRDIV8 and EDIV[5:0] effectively divides the EEPROM module input
oscillator clock down to a frequency of 150 kHz – 200 kHz. The maximum divide ratio is 512. Please refer to
Section 26.4.1.1, “Writing the ECLKDIV Register”
Enable Prescalar by 8
RESERVED1
RESERVED2
0
0
0
7
7
= Unimplemented or Reserved
= Unimplemented or Reserved
PRDIV8
Figure 26-4. EEPROM Clock Divider Register (ECLKDIV)
0
0
0
6
6
Table 26-3. ECLKDIV Field Descriptions
MC9S12XDP512 Data Sheet, Rev. 2.21
EDIV5
0
0
0
5
5
Figure 26-5. RESERVED1
EDIV4
0
0
0
4
4
Description
for more information.
EDIV3
Chapter 26 4 Kbyte EEPROM Module (S12XEETX4KV2)
0
0
0
3
3
EDIV2
0
0
0
2
2
EDIV1
0
0
0
1
1
EDIV0
0
0
0
0
0
1079
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