MC9S12XDT256CAA Freescale Semiconductor, MC9S12XDT256CAA Datasheet - Page 746

• Manufacturer Part Number: MC9S12XDT256CAA
• Description: IC MCU 256K FLASH 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XDT256CAA

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 59
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Processor Series: S12XD
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 59
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 20 S12X Debug (S12XDBGV3) Module
20.3
20.3.1
A summary of the registers associated with the S12XDBG sub-block is shown in
descriptions of the registers and bits are given in the subsections that follow.
748
Address
0x0028
0x0028
0x0020
0x0021
0x0022
0x0023
0x0024
0x0025
0x0026
0x0027
0x0027
0x0029
(See DUG)
(See DUG)
(See DUG)
Pin Name
TAGLO
TAGLO
TAGHI
1
2
Memory Map and Registers
(COMPB/D)
(COMPA/C)
DBGSCRX
DBGXCTL
DBGXCTL
DBGMFR
DBGTCR
DBGCNT
DBGXAH
DBGTBH
DBGTBL
Module Memory Map
DBGC1
DBGSR
DBGC2
Name
Tagging Enable
Pin Functions
Unconditional
W
W
W
W
W
W
W
W
W
W
W
W
R
R
R
R
R
R
R
R
R
R
R
R
Table 20-2. External System Pins Associated With S12XDBG
TAGLO
TAGHI
Bit 15
Bit 7
ARM
Figure 20-2. Quick Reference to S12XDBG Registers
Bit 7
TBF
SZE
0
0
0
0
0
0
TSOURCE
MC9S12XDP512 Data Sheet, Rev. 2.21
When instruction tagging is on, tags the high half of the instruction word being
read into the instruction queue.
When instruction tagging is on, tags the low half of the instruction word being
read into the instruction queue.
In emulation modes, a low assertion on this pin in the 7th or 8th cycle after the
end of reset enables the Unconditional Tagging function.
EXTF
Bit 14
Bit 22
TRIG
NDB
Bit 6
SZ
6
0
0
0
0
XGSBPE
Bit 13
Bit 5
TAG
TAG
21
5
0
0
0
0
TRANGE
Bit 12
BDM
Bit 4
BRK
BRK
20
4
0
0
0
0
Description
Bit 11
MC3
Bit 3
CNT
SC3
RW
RW
19
3
0
TRCMOD
DBGBRK
CDCM
Bit 10
SSF2
RWE
RWE
MC2
Bit 2
SC2
18
2
Table
Freescale Semiconductor
SSF1
20-2. Detailed
MC1
SRC
SRC
Bit 9
Bit 1
SC1
17
1
COMRV
TALIGN
ABCM
COMPE
COMPE
SSF0
Bit 16
Bit 0
MC0
Bit 8
Bit 0
SC0