MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 1092
MPC562MZP56
Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC562MZP56
Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
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Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No
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MPC562/MPC564 Compression Features
A.2.4
During the compression process, compressed instructions change their location in the memory and are not
word aligned. Displacement fields in the direct branch instructions have to be updated by the compression
tool to make compressed instruction addressing possible. Four LSB bits of the displacement immediate
field (LI or BD) in the compressed direct branch instructions are used for bit addressing in the 32-bit
memory word. The remaining bits of the fields are used in the branch target calculation of the base address
(word address). The RCPU branch unit copies the bit pointer into the IP field of issued compressed branch
target address. The branch compressed target base address is calculated according the direct branch
addressing mode.
If a branch has absolute addressing mode, the branch target base address is calculated as a sign extension
of the base address portion of the LI (or BD) field.
If a branch has relative addressing mode, the branch target base address is calculated as a sum of the base
address of the branch and sign extended base address portion of the branch LI (or BD) field.
Figure A-3
address for the unconditional branch has 20 bits This yields an unconditional branch displacement limit of
4 Mbytes. The word pointer for the conditional branch has 10 bits. This yields a conditional branch
displacement limit of 4 Kbytes.
A-4
illustrates direct branch target address generation in “Decompression On” mode. The base
Compressed Address Generation with Direct Branches
Compressed
Instruction
Adddress
Memory
Layout
– Compressed Instruction
Figure A-2. Addressing Instructions with Compressed Address
x+4
x+c
x+8
x
MPC561/MPC563 Reference Manual, Rev. 1.2
Base Address
2*IP Bits
Freescale Semiconductor
27
IP
31
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