MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 512

• Manufacturer Part Number: MPC562MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC562MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

QADC64E Legacy Mode Operation
To accommodate wide variations of the main MCU clock frequency (IMB3 clock — f
generated by a programmable prescaler which divides the MCU IMB3 clock to a frequency within the
specified QCLK tolerance range. To allow the A/D conversion time to be maximized across the spectrum
of IMB3 clock frequencies, the QADC64E prescaler permits the frequency of QCLK to be software
selectable. It also allows the duty cycle of the QCLK waveform to be programmable.
The software establishes the basic high phase of the QCLK waveform with the PSH (prescaler clock high
time) field in QACR0, and selects the basic low phase of QCLK with the prescaler clock low time (PSL)
field. The combination of the PSH and PSL parameters establishes the frequency of the QCLK.
13-48
Prescaler Rate Selection
(From Control Register 0):
Queue 1 & 2 Timer
Mode Rate Selection
IMB3 Clock
(F
High Time
Cycles (PSH)
Input Sample Time
from (CCW)
Low Time
Cycles (PSL)
SYS
)
A change in the prescaler value while a conversion is in progress is likely to
corrupt the result from any conversion in progress. Therefore, any prescaler
write operation should be done only when both queues are in the disabled
modes.
Figure 13-24. QADC64E Clock Subsystem Functions
5
Down Counter
8
One’s Complement
MPC561/MPC563 Reference Manual, Rev. 1.2
5-Bit
2
Compare
3
Detect
Zero
5
3
2 7
2 8
Load PSH
2 9
NOTE
2 10
PERIODIC/INTERVAL
Binary Counter
A/D Converter
State Machine
Timer Select
2 11
2 12
2 13
2 14
Reset QCLK
Set QCLK
2 15
2 16 2 17
(F
SYS
QADC64E Clock
/ 2 to F
Generate
Clock
10
2
SYS
//40 )
Freescale Semiconductor
SAR Control
SAR
SYS
Periodic / Interval
Trigger Event
for Q1 AND Q2
QCLK
), QCLK is