MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 194
MPC562MZP56
Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC562MZP56
Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
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Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No
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Central Processing Unit
3-50
1
Save/Restore Register 0 (SRR0)
Save/Restore Register 1 (SRR1)
If the exception occurs during an instruction fetch in Decompression On mode, the SRR0 register will contain a
compressed address.
Machine State Register (MSR)
Data/Storage Interrupt Status
Register (DSISR)
Register
Table 3-27. Register Settings for Alignment Exception
1
MPC561/MPC563 Reference Manual, Rev. 1.2
DCMPEN
[16:31]
[12:13]
[15:16]
[18:21]
[22:26]
[27:31]
[0:15]
Other
[0:11]
Bits
ME
LE
14
17
IP
Set to the effective address of the instruction that caused the
exception.
implementation, bit 30 of the SRR1 is never cleared, except by
loading a zero value from MSR[RI]
No change
Set to value of ILE bit prior to the exception
This bit is set according to (BBCMCR[EN_COMP] AND
BBCMCR[EXC_COMP])
Cleared to 0
For instructions that use register indirect with index addressing,
set to bits [29:30] of the instruction.
For instructions that use register indirect with immediate index
addressing, cleared.
set to bit 25 of the instruction.
For instructions that use register indirect with immediate index
addressing, set to bit 5 of the instruction.
For instructions that use register indirect with index addressing,
set to bits [21:24] of the instruction.
For instructions that use register indirect with immediate index
addressing, set to bits [1:4] of the instruction.
Set to bits [6:10] (source or destination) of the instruction.
Set to bits [11:15] of the instruction (rA). Set to either bits
[11:15] of the instruction or to any register number not in the
range of registers loaded by a valid form instruction, for lmw,
lswi, and lswx instructions. Otherwise undefined.
Cleared to 0
No change
Cleared to 0
Cleared to 0
Cleared to 0
For instructions that use register indirect with index addressing,
Loaded from bits [16:31] of MSR. In the current
Setting Description
Freescale Semiconductor
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