MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 395
MPC562MZP56
Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC562MZP56
Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
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Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No
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Note: the delay for the internal to external cycle may be one clock or greater.
9.5.14
Show cycles are representations of RCPU accesses to internal devices of the MPC561/MPC563. These
accesses are driven externally for emulation, visibility, and debugging purposes. A show cycle can have
one address phase and one data phase, or just an address phase in the case of instruction show cycles. The
cycle can be a write or a read access. The data for both the read and write accesses should be driven by the
bus master. (This is different from normal bus read and write accesses.) The address and data of the show
cycle must each be valid on the bus for one clock. The data phase must not require a transfer acknowledge
to terminate the bus show cycle.
Freescale Semiconductor
CLKOUT
BR
BG (output)
BB
ADDR[8:31]
RD/WR
TSIZ[0:1]
BURST
TS
Data
TA
RETRY (output)
Show Cycle Transactions
Figure 9-40. Retry of External Master Access (Internal Arbiter)
ADDR (external)
MPC561/MPC563 Reference Manual, Rev. 1.2
O
Allow Internal
Access to Gain the
Bus
ADDR (internal)
External Bus Interface
9-55
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