UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 194

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

5.7
cycle that is executed for each space selected by the chip select function in the multiplexed address/data bus mode.
In the separate bus mode, one idle state (TI) can be inserted after the T2 state. By inserting an idle state, the data
output float delay time of the memory can be secured during read access (an idle state cannot be inserted during
write access).
192
To facilitate interfacing with low-speed memories, one idle state (TI) can be inserted after the T3 state in the bus
Whether the idle state is to be inserted can be programmed by using the bus cycle control register (BCC).
An idle state is inserted for all the areas immediately after system reset.
(1) Bus cycle control register (BCC)
Caution Be sure to set bits 15, 13, 11, and 9 to 1, and clear bits 14, 12, 10, 8, 6, 4, 2, and 0 to 0.
Idle State Insertion Function
This register can be read or written in 16-bit units.
Cautions 1. The internal ROM, internal RAM, and internal peripheral I/O areas are not subject to idle
CSn signal
2. Write to the BCC register after reset, and then do not change the set values. Also, do not
After reset:
BCC
state insertion.
access an external memory area other than the one for this initialization routine until the
initial settings of the BCC register are complete. However, external memory areas whose
initial settings are complete may be accessed.
BC31
BCn1
CS3
15
AAAAH
1
0
1
7
Not inserted
Inserted
CHAPTER 5 BUS CONTROL FUNCTION
14
0
6
0
R/W
Specifies insertion of idle state (n = 0 to 3)
User’s Manual U15905EJ2V1UD
BC21
CS2
13
1
5
Address:
FFFFF48AH
12
0
0
4
BC11
CS1
11
1
3
10
0
2
0
BC01
CS0
1
9
1
0
0
8
0