UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 491

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

slaves.
V850ES/SA2 or V850ES/SA3. For details, refer to the PG-FP4 manual.
FLMD0
FLMD1
V
GND
CLK
RESET
SI/RxD
SO/TxD
SCK
HS
DD
(3) CSI0 + HS
The dedicated flash programmer outputs the transfer clock, and the V850ES/SA2 and V850ES/SA3 operate as
When the PG-FP4 is used as the dedicated flash programmer, it generates the following signals to the
Notes 1. Wire as shown in Figures 21-1 and 21-2, or connect to GND via a pull-down resistor on-board.
Remark
Signal Name
Serial clock: 2.4 kHz to 2.5 MHz (MSB first)
2. Connect when power is supplied from the PG-FP4.
3. Connect when the clock is supplied from the PG-FP4 (wire as shown in Figures 21-1 and 21-2, or
×:
generate an oscillator on-board to supply the clock).
: Always connected
Does not need to be connected
Figure 21-6. Communication with Dedicated Flash Programmer (CSI0 + HS)
Table 21-6. Signal Generation of Dedicated Flash Programmer (PG-FP4)
Dedicated flash
programmer
Output
Output
I/O
Output
Output
Input
Output
Output
Input
Bxxxxx
Cxxxxxx
Axxxx
I/O
−
PG-FP4
PG-FP4
STATVE
Mode setting, writing enable/
disable
Mode setting
V
voltage monitoring
Ground
Clock output to V850ES/SA2,
V850ES/SA3
Reset signal
Receive signal
Transmit signal
Transfer clock
Handshake signal of CSI0 + HS
DD
voltage generation/
CHAPTER 21 FLASH MEMORY
RESET
Pin Function
FLMD0,
FLMD1
User’s Manual U15905EJ2V1UD
GND
SCK
V
SO
HS
SI
DD
FLMD0
FLMD1
V
V
X1
RESET
SO0/TxD0
SI0/RxD0
SCK0
PDH0
V850ES/SA2,
V850ES/SA3
DD
SS
FLMD0,
FLMD1
V
RESET
SO0
SI0
SCK0
PDH0
V
Pin Name
SS
DD
V850ES/SA2,
V850ES/SA3
CSI0
×
×
Note 2
Note 3
×
Note 1
Connection Handling
UART0
×
×
Note 2
Note 3
×
×
Note 1
CSI0 + HS
×
×
Note 2
Note 3
Note 1
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