UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 284

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

282
(1) A/D converter mode register (ADM)
Notes 1. f
Caution Be sure to clear bits 6, 1, and 0 to 0.
Remark
This register sets the conversion time of the analog input signal to be converted into a digital signal as well as
conversion start and stop.
The ADM register can be read or written in 8-bit or 1-bit units.
This register is cleared to 00H after reset.
2. Be sure to clear the FR3 and FR2 bits to 00.
To use f
control register 0 (RTCC0) (refer to 9.2 (1)) to 0.
An A/D conversion operation can be used to output the f
power consumption, clear the CE bit of the prescaler mode register (PRSM) (refer to 6.5.1 (1)) and
ADCS bit of the ADM register to 0.
Refer to Tables 11-2 and 11-3 for examples of setting the A/D conversion time.
BRG
After reset:
ADM
output (refer to 6.5 Prescaler 3) is alternated with the main clock divider of the real-time counter.
BRG
ADCSB
ADCS
FR3
output as the conversion clock of the A/D converter, therefore, clear the CKS bit of RTC
00H
FR1
< >
0
1
0
0
1
1
0
0
1
1
Note 2
Note 1
Note 1
FR2
Stops conversion
Enables conversion
R/W
FR0
0
1
0
1
0
1
0
1
0
Note 2
CHAPTER 11 A/D CONVERTER
Address:
FR3
19 clocks
Setting prohibited
Setting prohibited
Setting prohibited
f
f
f
Clock of prescaler 3 (f
XX
XX
XX
User’s Manual U15905EJ2V1UD
/16
/8
/4
Note 2
FFFFF200H
Number of A/D conversion clocks
FR2
A/D conversion control
Note 2
A/D conversion clock
BRG
FR1
)
BRG
FR0
clock in the IDLE mode. To reduce the
0
0