UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 63

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(6) Exception/debug trap status saving registers (DBPC and DBPSW)
(7) CALLT base pointer (CTBP)
DBPSW
CTBP
DBPC
DBPC and DBPSW are exception/debug trap status registers.
If an exception trap or debug trap occurs, the contents of the program counter (PC) are saved to DBPC, and
those of the program status word (PSW) are saved to DBPSW.
The contents to be saved to DBPC are the address of the instruction next to the one that is executed when an
exception trap or debug trap occurs.
The current contents of the PSW are saved to DBPSW.
Bits 31 to 26 of DBPC and bits 31 to 8 of DBPSW are reserved for future function expansion (fixed to 0).
The CALLT base pointer (CTBP) is used to specify a table address or generate a target address (bit 0 is fixed
to 0).
Bits 31 to 26 of this register are reserved for future function expansion (fixed to 0).
31
0
31
31
0
0
0
0
0
0 0 0 0
0 0 0 0
0 0 0 0
26 25
26 25
0
0
0 0 0 0
CHAPTER 3 CPU FUNCTION
User’s Manual U15905EJ2V1UD
0
0
0 0 0 0
(Base address)
(Contents of PC)
0
0
0 0 0 0
8 7
(Contents of PSW)
0
0
0
0
(x: Undefined)
Default value
(x: Undefined)
(x: Undefined)
0xxxxxxxH
Default value
Default value
000000xxH
0xxxxxxxH
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