UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 316

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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(3) Continuous transmission operation
UARTn can write the next transmit data to the TXBn register at the timing that the transmit shift register starts
the shift operation. This enables an efficient transmission rate to be realized by continuously transmitting data
even during the INTSTn interrupt servicing after the transmission of one data frame. In addition, reading the
TXSFn bit of the ASIFn register after the occurrence of a transmission completion interrupt enables the TXBn
register to be efficiently written twice (2 bytes) without waiting for the transmission of 1 data frame.
When continuous transmission is performed, data should be written after referencing the ASIFn register to
confirm the transmission status and whether or not data can be written to the TXBn register.
Caution When transmission is performed continuously, write the first transmit data (first byte) to the
While transmission is being performed continuously, whether writing to the TXBn register later is enabled can
be judged by confirming the TXSFn bit after the occurrence of a transmission completion interrupt.
Cautions 1. When initializing the transmission unit when continuous transmission is completed,
TXBFn
TXSFn
0
1
0
1
TXBn register and confirm that the TXBFn bit is 0, and then write the next transmit data
(second byte) to TXBn register. If writing to the TXBn register is performed when the TXBFn
bit is 1, transmit data cannot be guaranteed.
2. While transmission is being performed continuously, an overrun error may occur if the
confirm that the TXBFn bit is 0 after the occurrence of the transmission completion
interrupt, and then execute initialization. If initialization is performed when the TXBFn bit
is 1, transmit data cannot be guaranteed.
next transmission is completed before the INTSTn interrupt servicing following the
transmission of 1 data frame is executed.
embedding a program that can count the number of transmit data and referencing the
TXSFn bit.
Writing is enabled
Writing is not enabled
Transmission is completed. However, the cautions concerning the TXBFn bit
must be observed. Writing transmit data can be performed twice (2 bytes).
Under transmission. Transmit data can be written once (1 byte).
CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE n (UARTn)
Whether or Not Writing to TXBn Register Is Enabled
User’s Manual U15905EJ2V1UD
Transmission Status
An overrun error can be detected by