UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 469

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

18.6 Subclock Operation Mode
18.6.1 Setting and operation status
normal operation mode.
subclock.
the system operates only with the subclock. However, watchdog timer stops counting when subclock operation is
started (CLS bit of PCC register = 1). (Watchdog timer retains the value before the subclock operation mode was
set.)
operation mode because the subclock is used as the internal system clock. In addition, the power consumption can
be further reduced to the level of the software STOP mode by stopping the operation of the main system clock
oscillator.
18.6.2 Releasing subclock operation mode
stopped (MCK bit = 1), set the MCK bit to 1, secure the oscillation stabilization time of the main clock by software, and
clear the CK3 bit to 0.
The subclock operation mode is set when the CK3 bit of the processor clock control register (PCC) is set to 1 in the
When the subclock operation mode is set, the internal system clock is changed from the main clock to the
When the MCK bit of the PCC register is set to 1, the operation of the main clock oscillator is stopped. As a result,
In the subclock operation mode, the power consumption can be reduced to a level lower than in the normal
Table 18-8 shows the operation status in subclock operation mode.
Caution When manipulating the CK3 bit, do not change the set values of the CK2 to CK0 bits of the PCC
The subclock operation mode is released by RESET pin input when the CK3 bit is cleared to 0. If the main clock is
The normal operation mode is restored when the subclock operation mode is released.
Caution When manipulating the CK3 bit, do not change the set values of the CK2 to CK0 bits (using a bit
register (using a bit manipulation instruction to manipulate the bit is recommended). For details
of the PCC register, refer to 6.3 (1) Processor clock control register (PCC).
manipulation instruction to manipulate the bit is recommended).
For details of the PCC register, refer to 6.3 (1) Processor clock control register (PCC).
CHAPTER 18 STANDBY FUNCTION
User’s Manual U15905EJ2V1UD
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