UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 273

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

10.2 Configuration
10.3 Control Registers
The watchdog timer consists of the following hardware.
The registers that control the watchdog timer are as follows.
• Oscillation stabilization time selection register (OSTS)
• Watchdog timer clock selection register (WDCS)
• Watchdog timer mode register (WDTM)
(1) Oscillation stabilization time selection register (OSTS)
Caution Set the oscillation stabilization time to 1.5 ms or longer.
This register selects the oscillation stabilization time following reset or release of the stop mode.
The OSTS register can be read or written in 8-bit units.
This register is set to 04H after reset.
OSTS
After reset:
Control register
OSTS2
Item
04H
0
0
0
0
0
1
1
1
1
Table 10-1. Configuration of Watchdog Timer
CHAPTER 10 WATCHDOG TIMER FUNCTIONS
R/W
OSTS1
0
0
0
1
1
0
0
1
1
Oscillation stabilization time selection register (OSTS)
Watchdog timer clock selection register (WDCS)
Watchdog timer mode register (WDTM)
Address:
OSTS0
User’s Manual U15905EJ2V1UD
0
0
1
0
1
0
1
0
1
FFFFF6C0H
2
2
2
2
2
2
2
2
14
16
17
18
19
20
21
22
/f
/f
/f
/f
/f
/f
/f
/f
0
X
X
X
X
X
X
X
X
Selection of oscillation stabilization time
Configuration
Setting
prohibited
3.28 ms
6.55 ms
13.1 ms
26.2 ms
52.4 ms
105 ms
210 ms
20 MHz
0
Setting
prohibited
3.855 ms
7.710 ms
15.42 ms
30.84 ms
61.68 ms
123.4 ms
246.7 ms
OSTS2
17 MHz
f
X
13.5 MHz
Setting
prohibited
4.855 ms
9.709 ms
19.42 ms
38.84 ms
77.67 ms
155.3 ms
310.7 ms
OSTS1
2.048 ms
8.192 ms
16.38 ms
32.77 ms
65.54 ms
131.1 ms
262.1 ms
524.3 ms
OSTS0
8 MHz
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